Is rs2 an ordinary data source operand for VSETVL?
No. The value in rs2 is interpreted as a full vtype configuration for SEW, LMUL, vta, vma, and related state.
VSETVL
RISC-V VSETVL Instruction Details
Instruction ManualOP-V vector configuration (register vtype)Configure vl/vtype from rs1/rd AVL rules and the full vtype value in rs2, then write the selected vl
Instruction Syntax
vsetvl rd, rs1, rs2
Operand Breakdown
rd, rs1 and rs2 are GPRs. All XLEN bits of rs2 supply vtype; x0 supplies 0 (e8,m1,tu,mu). Equal source registers read the same old value.
32-bit OP-V: bits[31:25]=1000000, followed by rs2, rs1, funct3=111, rd and opcode=1010111. No rs3 or v0.t. With rs1!=x0 AVL=x[rs1]; rs1=x0 with rd!=x0 requests VLMAX.
VLMAX=LMUL×VLEN/SEW. AVL≤VLMAX selects vl=AVL; VLMAX<AVL<2×VLMAX allows ceil(AVL/2)≤vl≤VLMAX; AVL≥2×VLMAX selects VLMAX. The same implementation is deterministic for equal AVL/VLMAX inputs.
rd=rs1=x0 uses current vl as AVL only when VLMAX is unchanged and prior vill=0; otherwise the use is reserved and an implementation may set vill. rd=x0 only discards GPR writeback.
Require V 1.0 and enabled vector state; vset does not depend on old vtype. Successful completion updates vl/vtype and clears vstart. Unsupported vtype sets vill, zeroes other vtype bits and vl; an implementation may instead trap to emulate illegal configurations.
VVector Configurationvset Instructions
Instruction Behavior
VSETVL is the register-vtype RVV configuration form. Like VSETVLI, it derives AVL from the rs1/rd combination. Ordinary AVL form: rs1 is nonzero, AVL=x[rs1]. VLMAX request form: rs1=x0, rd must be nonzero. Keep current vl form: rd=x0, rs1=x0, valid only when VLMAX is unchanged and prior vtype.vill=0. rs2 supplies the full vtype value, not textual assembly fields such as e32/m1/ta/ma. The instruction checks vtype under the official rules, selects the new vl, updates vl/vtype, and writes the selected vl to rd; successful execution resets vstart to zero.
VSETVL Decode And Execute Animation
Decode the vset fields, derive AVL and vtype, then show the architectural vl/vtype/rd update.
Step 1 / 6
Encoding
VSETVL is an OP-V configuration instruction. This step shows the opcode, funct3, and the fields carrying AVL/vtype information.
Instruction input
vsetvl
Execution Context
Scope: this animation shows only the ISA-visible vl/vtype selection rules from the V extension. Demo VLMAX and mid-range vl choice are educational inputs, not claims about a processor's VLEN, ELEN, support matrix, or OS handling.
Encoding fieldsvsetvl / OP-V
31..25
funct7
1000000
24..20
rs2
01011
19..15
rs1
01010
14..12
funct3
111
11..7
rd
00101
6..0
opcode
1010111
asm
form
VSETVL
Configuration data path
AVL source
x10
AVL
40
VLMAX
16
selected vl
16
vtype
e32, m1, ta, ma
x5
not written back
vstart
3
Current configuration summary
vl result
16
policy
ta/ma
vl selection result
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
The demo selects vl=16 from AVL=40 and VLMAX=16. Green cells show the body element range after configuration.
Assume V and the required vector state are enabled. This demo shows successful completion (using the vill path for unsupported configurations); an implementation may instead trap on illegal vtype to support emulation. Numeric AVL input is limited to exact nonnegative safe integers in an RV64 teaching context. Steps are explanatory, not hardware cycles.
Quick Understanding & Search Notes
VSETVL supplies vtype from a register instead of a vtypei immediate. It still derives AVL from the rs1/rd combination. Ordinary AVL form reads the requested element count from rs1. VLMAX request form: rs1=x0, rd must be nonzero. Keep current vl form: rd=x0, rs1=x0. This form is useful for restoring vector state from a full vtype value held in an integer register.
The OP-V opcode is 1010111 with funct3=111; rs2 supplies the full vtype value.
AVL is derived from the rs1/rd combination. Ordinary AVL form: rs1 nonzero, use x[rs1]. VLMAX request form: rs1=x0, rd must be nonzero. Keep current vl form: rd=x0, rs1=x0.
The official rules require all XLEN bits of the vtype value in rs2 to be checked, not just the low fields.
The rd=x0, rs1=x0 form requires unchanged VLMAX and prior vill=0; otherwise it is reserved and an implementation may set vill.
An ordinary unsupported configuration sets vill=1 and zeroes other vtype bits and vl; implementations may instead trap on illegal vtype for emulation.
Vector Execution Context
rd, rs1 and rs2 are GPRs. All XLEN bits of rs2 supply vtype; x0 supplies 0 (e8,m1,tu,mu). Equal source registers read the same old value.
32-bit OP-V: bits[31:25]=1000000, followed by rs2, rs1, funct3=111, rd and opcode=1010111. No rs3 or v0.t. With rs1!=x0 AVL=x[rs1]; rs1=x0 with rd!=x0 requests VLMAX.
VLMAX=LMUL×VLEN/SEW. AVL≤VLMAX selects vl=AVL; VLMAX<AVL<2×VLMAX allows ceil(AVL/2)≤vl≤VLMAX; AVL≥2×VLMAX selects VLMAX. The same implementation is deterministic for equal AVL/VLMAX inputs.
rd=rs1=x0 uses current vl as AVL only when VLMAX is unchanged and prior vill=0; otherwise the use is reserved and an implementation may set vill. rd=x0 only discards GPR writeback.
Require V 1.0 and enabled vector state; vset does not depend on old vtype. Successful completion updates vl/vtype and clears vstart. Unsupported vtype sets vill, zeroes other vtype bits and vl; an implementation may instead trap to emulate illegal configurations.
Common Usage Scenarios
Context Switch
Assume RV32/RV64 V, enabled vector state, supported e32,m1,ta,ma and VLEN=256, giving VLMAX=8. a0=8 and a1=0xD0 (full vtype, all other bits zero): successful execution of the example sets vl=t0=8 and vstart=0, without element masking.
Vector State Restore
Assume RV32/RV64 V, enabled vector state, supported e32,m1,ta,ma and VLEN=256, giving VLMAX=8. a0=8 and a1=0xD0 (full vtype, all other bits zero): successful execution of the example sets vl=t0=8 and vstart=0, without element masking.
Pre-Use Checklist
Syntax Check
- rd, rs1 and rs2 are GPRs. All XLEN bits of rs2 supply vtype; x0 supplies 0 (e8,m1,tu,mu). Equal source registers read the same old value.
- 32-bit OP-V: bits[31:25]=1000000, followed by rs2, rs1, funct3=111, rd and opcode=1010111. No rs3 or v0.t. With rs1!=x0 AVL=x[rs1]; rs1=x0 with rd!=x0 requests VLMAX.
Semantic Check
- VLMAX=LMUL×VLEN/SEW. AVL≤VLMAX selects vl=AVL; VLMAX<AVL<2×VLMAX allows ceil(AVL/2)≤vl≤VLMAX; AVL≥2×VLMAX selects VLMAX. The same implementation is deterministic for equal AVL/VLMAX inputs.
- rd=rs1=x0 uses current vl as AVL only when VLMAX is unchanged and prior vill=0; otherwise the use is reserved and an implementation may set vill. rd=x0 only discards GPR writeback.
- Require V 1.0 and enabled vector state; vset does not depend on old vtype. Successful completion updates vl/vtype and clears vstart. Unsupported vtype sets vill, zeroes other vtype bits and vl; an implementation may instead trap to emulate illegal configurations.
Pitfalls / Common Confusions
All XLEN bits of the vtype value in rs2 must be checked.
The rd=x0, rs1=x0 keep-vl form is only valid when VLMAX is unchanged and prior vill=0.
The vtype value comes from rs2; e32/m1/ta/ma are not written directly in the vsetvl assembly operands.
FAQ
Why is VSETVL useful for state restore?
Because save/restore code can place a saved vtype value in rs2 and use VSETVL to rebuild a consistent vl/vtype state.
Does VSETVL always take AVL from rs1?
No. Ordinary AVL form: rs1 nonzero, AVL=x[rs1]. VLMAX request form: rs1=x0, rd must be nonzero. Keep current vl form: rd=x0, rs1=x0.