Does VLE32.V automatically set vl?
No. vl/vtype are set by an earlier vsetvli, vsetivli, or vsetvl; vector loads and stores execute under the current configuration.
VLE32.V
RISC-V VLE32.V Instruction Details
Instruction ManualV-typeLoad 32-bit elements into vd from x[rs1] with unit stride.
Instruction Syntax
vle32.v vd, (rs1), vm
Operand Breakdown
vd receives EEW=32-bit memory bit patterns; EMUL=(EEW/SEW)×LMUL must be in 1/8..8 with a legal register-group start. Elements are not extended into XLEN-wide scalars.
rs1 is an integer base register; element i uses x[rs1]+i×4 bytes, with base 0 for rs1=x0. v0.t gives vm=0; omitting it gives vm=1.
Require enabled V and valid vtype. Active body elements satisfy vstart≤i<vl and mask enabled; masked vd cannot cover v0. Disabled elements access no memory; inactive/tail follow vma/vta and prestart stays unchanged. VL=0 or vstart≥vl updates no destination.
This instruction executes under current vl without changing it; normal completion resets vstart=0. Misalignment may succeed or raise an address-misaligned exception; unit stride guarantees no element access order.
VVector MemoryVector Load
Instruction Behavior
VLE32.V is a RISC-V V 32-bit unit-stride vector load. Active body elements read memory elements from consecutive addresses x[rs1] + i * 4 bytes and write vd; with vm=0, v0.t selects elements and masked-off elements do not access memory.
VLE32.V Decode And Execute Animation
Decode the 32-bit unit-stride load, then compute each element address as x[rs1] + i * 4.
Instruction input
vle32.v
Execution context: EEW=32, unit stride=4 bytes, example SEW=32, LMUL=m1, vstart=0 (a nonzero value starts at that element). These are not assembly syntax operands.
Teaching context: VLEN=4096, SEW=EEW=32, LMUL=EMUL=m1, VLMAX=128, vstart=0, valid vtype, enabled VS, and ta/ma. Base options are naturally aligned; rs1=x0 fixes the base at 0. Only the selected synchronous-fault scenario is modeled, assuming other selected memory is readable; actual system accessibility is not guaranteed. Per-element steps explain addresses and results, not access order or processor cycles. Inactive/tail elements may retain old values or become all ones; no definite result is shown. Normal completion resets vstart=0.
Encoding fieldsvle32.v / LOAD-FP
31..29
nf
000
28
mew
0
27..26
mop
00
25
vm
0
24..20
lumop
00000
19..15
rs1
01010
14..12
width
110
11..7
vd/vs3
01000
6..0
opcode
0000111
Address and data pathaddr[i] = 0x8000 + i * 4
i=0
i=1
i=2
i=3
i=4
i=5
i=6
i=7
i=8
i=9
i=10
i=11
i=12
i=13
i=14
i=15
addr
0x8000
0x8004
0x8008
0x800c
0x8010
0x8014
0x8018
0x801c
0x8020
0x8024
0x8028
0x802c
0x8030
0x8034
0x8038
0x803c
mem
0x00000101
0x00000202
0x00000303
0x00000404
0x00000505
0x00000606
0x00000707
0x00000808
0x00000909
0x00000a0a
0x00000b0b
0x00000c0c
0x00000d0d
0x00000e0e
0x00000f0f
0x00001010
active
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
v8
...
...
-
...
...
...
...
-
...
...
...
...
-
...
...
...
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Show vector memory instruction encoding
The animation starts from the 32-bit vector memory encoding and shows the official bit fields: nf, mew, mop, vm, rs2/vs2 or lumop/sumop, width, register fields, and opcode.
Quick Understanding & Search Notes
VLE32.V is an RVV 32-bit unit-stride vector load: each active element uses address x[rs1] + i * 4 bytes to read from memory, and element data is written into destination vector register group vd. vl and the v0.t mask decide which body elements actually access memory.
The mnemonic fixes memory element width EEW=32; unit-stride addresses advance by EEW/8 bytes, not by an arbitrary index scale or by the textual SEW alone.
The unit-stride form starts at x[rs1] and accesses consecutive element addresses; strided and indexed/gather/scatter access use other families such as vlse/vsse, vluxei/vloxei, and vsuxei/vsoxei.
With vm=0, v0.t selects participating body elements; with vm=1, all body elements participate. Masked-off elements do not perform memory accesses.
Active elements receive memory bit patterns without scalar-style sign extension. Inactive/tail elements follow vma/vta, preserving old values or permitting all ones; prestart elements stay undisturbed.
Data EEW=32 and EMUL=(EEW/SEW)×LMUL. EMUL must lie in 1/8 through 8, with a legal starting vd for that group. A masked load destination group must not overlap v0.
A misaligned element may transfer successfully or raise an address-misaligned exception; scalar misalignment support does not imply vector support. Unit-stride element accesses have no guaranteed order.
Body elements satisfy vstart≤i<vl; prestart elements stay undisturbed. VL=0 or vstart≥vl updates no destination elements, including tails. Normal completion resets vstart=0; V must be enabled and vtype valid.
Vector Execution Context
vd receives EEW=32-bit memory bit patterns; EMUL=(EEW/SEW)×LMUL must be in 1/8..8 with a legal register-group start. Elements are not extended into XLEN-wide scalars.
rs1 is an integer base register; element i uses x[rs1]+i×4 bytes, with base 0 for rs1=x0. v0.t gives vm=0; omitting it gives vm=1.
Require enabled V and valid vtype. Active body elements satisfy vstart≤i<vl and mask enabled; masked vd cannot cover v0. Disabled elements access no memory; inactive/tail follow vma/vta and prestart stays unchanged. VL=0 or vstart≥vl updates no destination.
This instruction executes under current vl without changing it; normal completion resets vstart=0. Misalignment may succeed or raise an address-misaligned exception; unit stride guarantees no element access order.
Common Usage Scenarios
Contiguous Array Read
Assume enabled V/VS, valid e32,m1, VLMAX≥4, AVL=4, and vl=4, vstart=0, ta/ma after vsetvli; destination does not overlap source masks. Memory is readable except for the selected fault; address step=4 bytes: a0=0x8000, v0=[1,0,1,1], mem=[10,20,30,40] → vd=[10,agnostic,30,40]. Agnostic elements may retain old values or become all ones, without guaranteed zeros.
Vectorized Memory Access
Assume enabled V/VS, valid e32,m1, VLMAX≥4, AVL=4, and vl=4, vstart=0, ta/ma after vsetvli; destination does not overlap source masks. Memory is readable except for the selected fault; address step=4 bytes: a0=0x8000, v0=[1,0,1,1], mem=[10,20,30,40] → vd=[10,agnostic,30,40]. Agnostic elements may retain old values or become all ones, without guaranteed zeros.
Pre-Use Checklist
Syntax Check
- vd receives EEW=32-bit memory bit patterns; EMUL=(EEW/SEW)×LMUL must be in 1/8..8 with a legal register-group start. Elements are not extended into XLEN-wide scalars.
- rs1 is an integer base register; element i uses x[rs1]+i×4 bytes, with base 0 for rs1=x0. v0.t gives vm=0; omitting it gives vm=1.
Semantic Check
- Require enabled V and valid vtype. Active body elements satisfy vstart≤i<vl and mask enabled; masked vd cannot cover v0. Disabled elements access no memory; inactive/tail follow vma/vta and prestart stays unchanged. VL=0 or vstart≥vl updates no destination.
- This instruction executes under current vl without changing it; normal completion resets vstart=0. Misalignment may succeed or raise an address-misaligned exception; unit stride guarantees no element access order.
Pitfalls / Common Confusions
The 32 in the mnemonic is memory element width EEW; the address step is 4 bytes.
Unit-stride access uses consecutive addresses; do not treat it as indexed gather/scatter.
Masked-off elements do not perform memory reads, and destination elements follow the current mask policy.
FAQ
How are unit-stride load addresses calculated?
Active element i uses x[rs1] + i * 4 bytes. This is contiguous memory access, not arbitrary gather/scatter.
Do elements disabled by v0.t access memory?
No. With vm=0, a body element whose v0.t bit is 0 does not perform that element's load memory access.