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VLE64.V

RISC-V VLE64.V Instruction Details

Instruction ManualV-type

Load 64-bit elements into vd from x[rs1] with unit stride.

Instruction Syntax

vle64.v vd, (rs1), vm

Operand Breakdown

vd: destination vector register group receiving loaded active elements.

rs1: integer base-address register; unit-stride forms read elements from consecutive addresses.

vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.

VVector MemoryVector Load

Related Search Terms

VLE64.V instruction RISC-V VLE64.V vle64.v syntax vle64.v encoding RVV unit-stride load 64-bit vector load vle64.v mask behavior

Instruction Behavior

VLE64.V is a RISC-V V 64-bit unit-stride vector load. Active body elements read memory elements from consecutive addresses x[rs1] + i * 8 bytes and write vd; with vm=0, v0.t selects elements and masked-off elements do not access memory.

VLE64.V Decode And Execute Animation

Decode the 64-bit unit-stride load, then compute each element address as x[rs1] + i * 8.

Instruction input

vle64.v

vdVector register v0-v31rs1Integer base-address registervmexecution mask control

VLx[rs1]memory elements0..0xffffffffffffffff, comma-separatedv0 mask bits0/1 only, length equals VL

Execution context: EEW=64, unit stride=8 bytes, example SEW=64, LMUL=m1. These are not assembly syntax operands.

Encoding fieldsvle64.v / LOAD-FP

31..29

000

mew

27..26

mop

24..20

lumop

00000

19..15

rs1

01010

14..12

width

111

11..7

vd/vs3

01000

6..0

opcode

0000111

Address and data pathaddr[i] = 0x8000 + i * 8

i=0

i=1

i=2

i=3

i=4

i=5

i=6

i=7

i=8

i=9

i=10

i=11

i=12

i=13

i=14

i=15

addr

0x8000

0x8008

0x8010

0x8018

0x8020

0x8028

0x8030

0x8038

0x8040

0x8048

0x8050

0x8058

0x8060

0x8068

0x8070

0x8078

mem

0x0000000000001003

0x0000000000002006

0x0000000000003009

0x000000000000400c

0x000000000000500f

0x0000000000006012

0x0000000000007015

0x0000000000008018

0x000000000000901b

0x000000000000a01e

0x000000000000b021

0x000000000000c024

0x000000000000d027

0x000000000000e02a

0x000000000000f02d

0x0000000000010030

active

...

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Show vector memory instruction encoding

The animation starts from the 32-bit vector memory encoding and shows the official bit fields: nf, mew, mop, vm, rs2/vs2 or lumop/sumop, width, register fields, and opcode.

Quick Understanding & Search Notes

VLE64.V is an RVV 64-bit unit-stride vector load: each active element uses address x[rs1] + i * 8 bytes to read from memory, and element data is written into destination vector register group vd. vl and the v0.t mask decide which body elements actually access memory.

The mnemonic fixes memory element width EEW=64; unit-stride addresses advance by EEW/8 bytes, not by an arbitrary index scale or by the textual SEW alone.

The unit-stride form starts at x[rs1] and accesses consecutive element addresses; strided and indexed/gather/scatter access use other families such as vlse/vsse, vluxei/vloxei, and vsuxei/vsoxei.

With vm=0, v0.t selects participating body elements; with vm=1, all body elements participate. Masked-off elements do not perform memory accesses.

Loads update only active destination elements; inactive and tail destination elements follow the current vtype mask/tail policies.

RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations

Vector Execution Context

When reading VLE64.V, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Contiguous Array Read

Understand this scenario with real code like «vle64.v v8, (a0), v0.t».

Vectorized Memory Access

Understand this scenario with real code like «vle64.v v8, (a0), v0.t».

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is V-type.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

The 64 in the mnemonic is memory element width EEW; the address step is 8 bytes.

Unit-stride access uses consecutive addresses; do not treat it as indexed gather/scatter.

Masked-off elements do not perform memory reads, and destination elements follow the current mask policy.

FAQ

Does VLE64.V automatically set vl?

No. vl/vtype are set by an earlier vsetvli, vsetivli, or vsetvl; vector loads and stores execute under the current configuration.

How are unit-stride load addresses calculated?

Active element i uses x[rs1] + i * 8 bytes. This is contiguous memory access, not arbitrary gather/scatter.

Do elements disabled by v0.t access memory?

No. With vm=0, a body element whose v0.t bit is 0 does not perform that element's load memory access.