VLSE64.V

RISC-V VLSE64.V Instruction Details

Q: What unit does VLSE64.V use for stride?

The stride is the byte count in x[rs2]. It is not an element count and is not implicitly multiplied by EEW again; if encoded as rs2=x0, x0 is always 0.

Q: How is VLSE64.V different from unit-stride VLE64.V?

Unit-stride access advances by consecutive 8-byte elements; VLSE64.V uses byte stride x[rs2], so it can access structure fields, matrix columns, or reverse sequences.

Q: Is rs2=x0 different from x[rs2]=0 for VLSE64.V?

Yes. rs2=x0 directly encodes the x0 zero-stride form; the ISA permits implementations to perform fewer than one memory operation per active element for that form. If rs2 is not x0 but its register value is 0, the ordinary strided-access semantics still apply.

Q: Do elements disabled by v0.t access memory?

No. With vm=0, a body element whose v0.t bit is 0 does not perform that element's load memory access.

Instruction ManualV-type

Load 64-bit vector elements into vd using byte stride x[rs2] from base x[rs1].

Instruction Syntax

vlse64.v vd, (rs1), rs2, vm

Operand Breakdown

Syntax: vlse64.v vd, (rs1), rs2[, v0.t]; omitted v0.t gives vm=1, included gives vm=0. vd is a vector group, rs1 an integer base register, with base 0 for x0. 32-bit LOAD-FP: opcode=0000111, nf=000, mew=0, mop=10, width=111.

Data EEW=64, EMUL=(64/SEW)×LMUL. rs2 selects an integer register; address=x[rs1]+i×x[rs2]. The byte stride may be positive, negative, or zero, without scaling by 8.

The data width must be supported, EMUL in 1/8..8, and group starts legal. rs2=x0 permits fewer accesses than active elements; rs2≠x0 with value 0 requires one access per active element.

V 1.0 supports RV32/RV64; require valid vtype and enabled VS. Only elements with vstart≤i<vl and enabled masks access memory; masked vd cannot overlap v0. Prestart stays unchanged, inactive/tail follow vma/vta, and agnostic elements may retain old values or become all ones.

These strided and unordered indexed forms do not guarantee element access order. Misalignment may succeed or raise an address-misaligned exception; addresses must also satisfy access permissions. VL=0 or vstart≥vl updates no destination; normal completion resets vstart=0 and leaves vl unchanged.

VVector MemoryVector Load

Related Search Terms

VLSE64.V instruction RISC-V VLSE64.V vlse64.v syntax vlse64.v encoding RVV strided load 64-bit vector load vlse64.v byte stride

Instruction Behavior

VLSE64.V is a RISC-V V 64-bit strided vector load. Active body elements use address x[rs1] plus the lane index times x[rs2]; x[rs2] is a byte-count stride and may represent positive, negative, or zero stride. With vm=0, v0.t selects elements, and masked-off elements do not access memory.

VLSE64.V Decode And Execute Animation

Decode the 64-bit strided load, then compute each element address as x[rs1] + i * x[rs2] (16 bytes).

Instruction input

vlse64.v

vdVector register v0-v31rs1Integer base-address registerrs2Integer stride registervmexecution mask control

VLx[rs1]x[rs2] stride bytesTeaching range, not an ISA limit: -32768..32768 bytes, including negative and zeromemory elements0..0xffffffffffffffff, comma-separatedv0 mask bits0/1 only, length equals VL

Execution context: EEW=64, stride=x[rs2]=16 bytes, example SEW=64, LMUL=m1, vstart=0 (a nonzero value starts at that element). These are not assembly syntax operands.

Teaching context: XLEN=64, VLEN=4096, SEW=64, LMUL=m1, VLMAX=64, data EMUL=m1, valid vtype, enabled VS, vstart=0, and ta/ma. All selected accesses are assumed successful; traps are not modeled. Unaligned accesses apply only where the environment supports them. rs1=x0 fixes the base at 0. The memory elements input gives the value observed by each active read, allowing memory to change between accesses; it is not a static byte-memory image. The rs2=x0 example selects the permitted execution with one read per active element. Per-element steps do not represent processor cycles or actual access order; strided accesses are unordered. Inactive/tail “-” means the result is not shown and may retain the old value or become all ones. VL=0 leaves the destination unchanged; normal completion resets vstart=0.

Encoding fieldsvlse64.v / LOAD-FP

31..29

000

mew

27..26

mop

24..20

rs2

00101

19..15

rs1

01010

14..12

width

111

11..7

vd/vs3

01000

6..0

opcode

0000111

Address and data pathaddr[i] = 0x8000 + i * 16

i=0

i=1

i=2

i=3

i=4

i=5

i=6

i=7

i=8

i=9

i=10

i=11

i=12

i=13

i=14

i=15

addr

0x8000

0x8010

0x8020

0x8030

0x8040

0x8050

0x8060

0x8070

0x8080

0x8090

0x80a0

0x80b0

0x80c0

0x80d0

0x80e0

0x80f0

mem

0x0000000000001003

0x0000000000002006

0x0000000000003009

0x000000000000400c

0x000000000000500f

0x0000000000006012

0x0000000000007015

0x0000000000008018

0x000000000000901b

0x000000000000a01e

0x000000000000b021

0x000000000000c024

0x000000000000d027

0x000000000000e02a

0x000000000000f02d

0x0000000000010030

active

...

Step 1 / 22

Show vector memory instruction encoding

The animation starts from the 32-bit vector memory encoding and shows the official bit fields: nf, mew, mop, vm, rs2/vs2 or lumop/sumop, width, register fields, and opcode.

Quick Understanding & Search Notes

VLSE64.V is an RVV 64-bit strided vector load: each active element uses memory address x[rs1] plus the lane index times x[rs2], where x[rs2] is a byte stride. vl and the v0.t mask decide which body elements participate in memory access.

The mnemonic fixes memory element width EEW=64; stride comes from integer register x[rs2], is measured in bytes, and is not implicitly scaled by EEW.

Strided access uses one scalar stride to generate the address sequence; indexed gather/scatter uses other families such as vluxei/vloxei or vsuxei/vsoxei.

x[rs2] may represent positive, negative, or zero stride; when the encoded rs2 field is x0, x0 is always 0 and the ISA permits implementations to perform fewer than one memory operation per active element for this zero-stride form.

With vm=0, v0.t selects participating body elements; with vm=1, all body elements participate. Masked-off elements do not perform memory accesses.

Loads update only active destination elements; inactive and tail destination elements follow the current vtype mask/tail policies.

V 1.0: RV32/RV64, valid vtype, enabled VS; EMUL=1/8..8 and legal group starts. Only active vstart≤i<vl elements access memory. VL=0 leaves destinations unchanged; normal completion resets vstart=0, preserving vl. Misalignment may succeed or trap.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture

Vector Execution Context

Data EEW=64, EMUL=(64/SEW)×LMUL. rs2 selects an integer register; address=x[rs1]+i×x[rs2]. The byte stride may be positive, negative, or zero, without scaling by 8.

The data width must be supported, EMUL in 1/8..8, and group starts legal. rs2=x0 permits fewer accesses than active elements; rs2≠x0 with value 0 requires one access per active element.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, Chapter 31

Common Usage Scenarios

Structure field access

Assume enabled V/VS, supported widths, VLEN≥256, x10=0x8000, x11=4, and successful memory accesses; vsetvli gives vl=4, vstart=0, ta/ma. e64,m1; x5=32; v0.mask=[1,0,1,1]; addresses=[0x8000,0x8020,0x8040,0x8060]; active reads (i=0,2,3)=[10,30,40] → v8=[10,agnostic,30,40]. Disabled elements make no memory access. Agnostic elements may retain old values or become all ones; tails are not guaranteed zero. The address list is not an access-order guarantee.

Matrix row or column stride access

Non-contiguous vector reads

Pre-Use Checklist

Syntax Check

Syntax: vlse64.v vd, (rs1), rs2[, v0.t]; omitted v0.t gives vm=1, included gives vm=0. vd is a vector group, rs1 an integer base register, with base 0 for x0. 32-bit LOAD-FP: opcode=0000111, nf=000, mew=0, mop=10, width=111.
Data EEW=64, EMUL=(64/SEW)×LMUL. rs2 selects an integer register; address=x[rs1]+i×x[rs2]. The byte stride may be positive, negative, or zero, without scaling by 8.

Semantic Check

The data width must be supported, EMUL in 1/8..8, and group starts legal. rs2=x0 permits fewer accesses than active elements; rs2≠x0 with value 0 requires one access per active element.
V 1.0 supports RV32/RV64; require valid vtype and enabled VS. Only elements with vstart≤i<vl and enabled masks access memory; masked vd cannot overlap v0. Prestart stays unchanged, inactive/tail follow vma/vta, and agnostic elements may retain old values or become all ones.
These strided and unordered indexed forms do not guarantee element access order. Misalignment may succeed or raise an address-misaligned exception; addresses must also satisfy access permissions. VL=0 or vstart≥vl updates no destination; normal completion resets vstart=0 and leaves vl unchanged.

Pitfalls / Common Confusions

The 64 in the mnemonic is memory element width EEW; the address increment comes from byte-count x[rs2] and is not implicitly scaled again by 8.

The stride may be positive, negative, or zero; rs2=x0 is the official zero-stride encoding, x0 is always 0, and implementations may perform fewer than one memory operation per active element for that form.

Masked-off elements do not perform memory reads, and destination elements follow the current mask policy.

Do not rely on element access order to express side-effecting memory or overlapping-address semantics.

FAQ

What unit does VLSE64.V use for stride?