Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VLSE64.V
RISC-V VLSE64.V Instruction Details
Instruction ManualV-typeLoad 64-bit vector elements into vd using byte stride x[rs2] from base x[rs1].
Instruction Syntax
vlse64.v vd, (rs1), rs2, vm
Operand Breakdown
vd: destination vector register group receiving loaded active elements.
rs1: integer base-address register; unit-stride forms read elements from consecutive addresses.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector MemoryVector Load
Instruction Behavior
VLSE64.V is a RISC-V V 64-bit strided vector load. Active body elements use address x[rs1] plus the lane index times x[rs2]; x[rs2] is a byte-count stride and may represent positive, negative, or zero stride. With vm=0, v0.t selects elements, and masked-off elements do not access memory.
VLSE64.V Decode And Execute Animation
Decode the 64-bit strided load, then compute each element address as x[rs1] + i * x[rs2] (16 bytes).
Instruction input
vlse64.v
Execution context: EEW=64, stride=x[rs2]=16 bytes, example SEW=64, LMUL=m1. These are not assembly syntax operands.
Encoding fieldsvlse64.v / LOAD-FP
31..29
nf
000
28
mew
0
27..26
mop
10
25
vm
0
24..20
rs2
00101
19..15
rs1
01010
14..12
width
111
11..7
vd/vs3
01000
6..0
opcode
0000111
Address and data pathaddr[i] = 0x8000 + i * 16
i=0
i=1
i=2
i=3
i=4
i=5
i=6
i=7
i=8
i=9
i=10
i=11
i=12
i=13
i=14
i=15
addr
0x8000
0x8010
0x8020
0x8030
0x8040
0x8050
0x8060
0x8070
0x8080
0x8090
0x80a0
0x80b0
0x80c0
0x80d0
0x80e0
0x80f0
mem
0x0000000000001003
0x0000000000002006
0x0000000000003009
0x000000000000400c
0x000000000000500f
0x0000000000006012
0x0000000000007015
0x0000000000008018
0x000000000000901b
0x000000000000a01e
0x000000000000b021
0x000000000000c024
0x000000000000d027
0x000000000000e02a
0x000000000000f02d
0x0000000000010030
active
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
v8
...
...
-
...
...
...
...
-
...
...
...
...
-
...
...
...
Step 1 / 22
Show vector memory instruction encoding
The animation starts from the 32-bit vector memory encoding and shows the official bit fields: nf, mew, mop, vm, rs2/vs2 or lumop/sumop, width, register fields, and opcode.
Quick Understanding & Search Notes
VLSE64.V is an RVV 64-bit strided vector load: each active element uses memory address x[rs1] plus the lane index times x[rs2], where x[rs2] is a byte stride. vl and the v0.t mask decide which body elements participate in memory access.
The mnemonic fixes memory element width EEW=64; stride comes from integer register x[rs2], is measured in bytes, and is not implicitly scaled by EEW.
Strided access uses one scalar stride to generate the address sequence; indexed gather/scatter uses other families such as vluxei/vloxei or vsuxei/vsoxei.
x[rs2] may represent positive, negative, or zero stride; when the encoded rs2 field is x0, x0 is always 0 and the ISA permits implementations to perform fewer than one memory operation per active element for this zero-stride form.
With vm=0, v0.t selects participating body elements; with vm=1, all body elements participate. Masked-off elements do not perform memory accesses.
Loads update only active destination elements; inactive and tail destination elements follow the current vtype mask/tail policies.
Vector Execution Context
When reading VLSE64.V, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Structure field access
Understand this scenario with real code like «li t0, 32 vsetvli t1, a2, e64, m1, ta, ma vlse64.v v8, (a0), t0, v0.t».
Matrix row or column stride access
Understand this scenario with real code like «li t0, 32 vsetvli t1, a2, e64, m1, ta, ma vlse64.v v8, (a0), t0, v0.t».
Non-contiguous vector reads
Understand this scenario with real code like «li t0, 32 vsetvli t1, a2, e64, m1, ta, ma vlse64.v v8, (a0), t0, v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is V-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
The 64 in the mnemonic is memory element width EEW; the address increment comes from byte-count x[rs2] and is not implicitly scaled again by 8.
The stride may be positive, negative, or zero; rs2=x0 is the official zero-stride encoding, x0 is always 0, and implementations may perform fewer than one memory operation per active element for that form.
Masked-off elements do not perform memory reads, and destination elements follow the current mask policy.
Do not rely on element access order to express side-effecting memory or overlapping-address semantics.
FAQ
What unit does VLSE64.V use for stride?
The stride is the byte count in x[rs2]. It is not an element count and is not implicitly multiplied by EEW again; if encoded as rs2=x0, x0 is always 0.
How is VLSE64.V different from unit-stride VLE64.V?
Unit-stride access advances by consecutive 8-byte elements; VLSE64.V uses byte stride x[rs2], so it can access structure fields, matrix columns, or reverse sequences.
Is rs2=x0 different from x[rs2]=0 for VLSE64.V?
Yes. rs2=x0 directly encodes the x0 zero-stride form; the ISA permits implementations to perform fewer than one memory operation per active element for that form. If rs2 is not x0 but its register value is 0, the ordinary strided-access semantics still apply.
Do elements disabled by v0.t access memory?
No. With vm=0, a body element whose v0.t bit is 0 does not perform that element's load memory access.