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VLSE8.V

RISC-V VLSE8.V Instruction Details

Instruction ManualR-type

Load 8-bit elements into vd from x[rs1] using byte stride x[rs2].

Instruction Syntax

vlse8.v vd, (rs1), rs2, vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
VVector LoadMemory Access
Related Search Terms
VLSE8.V instructionRISC-V VLSE8.Vvlse8.v syntaxvlse8.v RVV8-bit loadstrided load

Instruction Behavior

VLSE8.V is a RISC-V V 8-bit strided vector load instruction. Each active element address is x[rs1] + i * x[rs2], with the stride measured in bytes. It operates on active elements within vl, with masking and tail behavior following RVV rules.

Quick Understanding & Search Notes

The stride comes from integer register rs2 and is measured in bytes, so negative and zero strides are represented by that register value.

EEW=8; destination elements are interpreted under the current SEW/LMUL configuration and instruction EEW rules.
The stride is a byte count from x[rs2], not implicitly scaled by element width.
vm=0 uses v0 as the execution mask and vm=1 is unmasked; inactive and tail elements follow the current vma/vta policy.
RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations

Common Usage Scenarios

Matrix Ops

Understand this scenario with real code like «li t1, 4 vsetvli t0, a0, e8, m1, ta, ma vlse8.v v1, (a0), t1».

Strided Arrays

Understand this scenario with real code like «li t1, 4 vsetvli t0, a0, e8, m1, ta, ma vlse8.v v1, (a0), t1».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Stride in rs2 (byte units, can be negative). EEW is fixed at 8.
Stride is scalar register value (dynamic). Differs from vle in variable inter-element increment.

FAQ

What unit is used for VLSE8.V address offsets?

Strided-load rs2 is a byte stride.

How does VLSE8.V handle masking?

With vm=0, v0 selects active elements; with vm=1, all body elements participate. Inactive and tail elements follow the current policies.