What unit does VLSE8.V use for stride?
The stride is the byte count in x[rs2]. It is not an element count and is not implicitly multiplied by EEW again; if encoded as rs2=x0, x0 is always 0.
VLSE8.V
RISC-V VLSE8.V Instruction Details
Instruction ManualV-typeLoad 8-bit vector elements into vd using byte stride x[rs2] from base x[rs1].
Instruction Syntax
vlse8.v vd, (rs1), rs2, vm
Operand Breakdown
Syntax: vlse8.v vd, (rs1), rs2[, v0.t]; omitted v0.t gives vm=1, included gives vm=0. vd is a vector group, rs1 an integer base register, with base 0 for x0. 32-bit LOAD-FP: opcode=0000111, nf=000, mew=0, mop=10, width=000.
Data EEW=8, EMUL=(8/SEW)×LMUL. rs2 selects an integer register; address=x[rs1]+i×x[rs2]. The byte stride may be positive, negative, or zero, without scaling by 1.
The data width must be supported, EMUL in 1/8..8, and group starts legal. rs2=x0 permits fewer accesses than active elements; rs2≠x0 with value 0 requires one access per active element.
V 1.0 supports RV32/RV64; require valid vtype and enabled VS. Only elements with vstart≤i<vl and enabled masks access memory; masked vd cannot overlap v0. Prestart stays unchanged, inactive/tail follow vma/vta, and agnostic elements may retain old values or become all ones.
These strided and unordered indexed forms do not guarantee element access order. Misalignment may succeed or raise an address-misaligned exception; addresses must also satisfy access permissions. VL=0 or vstart≥vl updates no destination; normal completion resets vstart=0 and leaves vl unchanged.
VVector MemoryVector Load
Instruction Behavior
VLSE8.V is a RISC-V V 8-bit strided vector load. Active body elements use address x[rs1] plus the lane index times x[rs2]; x[rs2] is a byte-count stride and may represent positive, negative, or zero stride. With vm=0, v0.t selects elements, and masked-off elements do not access memory.
VLSE8.V Decode And Execute Animation
Decode the 8-bit strided load, then compute each element address as x[rs1] + i * x[rs2] (16 bytes).
Instruction input
vlse8.v
Execution context: EEW=8, stride=x[rs2]=16 bytes, example SEW=8, LMUL=m1, vstart=0 (a nonzero value starts at that element). These are not assembly syntax operands.
Teaching context: XLEN=64, VLEN=4096, SEW=8, LMUL=m1, VLMAX=512, data EMUL=m1, valid vtype, enabled VS, vstart=0, and ta/ma. All selected accesses are assumed successful; traps are not modeled. Unaligned accesses apply only where the environment supports them. rs1=x0 fixes the base at 0. The memory elements input gives the value observed by each active read, allowing memory to change between accesses; it is not a static byte-memory image. The rs2=x0 example selects the permitted execution with one read per active element. Per-element steps do not represent processor cycles or actual access order; strided accesses are unordered. Inactive/tail “-” means the result is not shown and may retain the old value or become all ones. VL=0 leaves the destination unchanged; normal completion resets vstart=0.
Encoding fieldsvlse8.v / LOAD-FP
31..29
nf
000
28
mew
0
27..26
mop
10
25
vm
0
24..20
rs2
00101
19..15
rs1
01010
14..12
width
000
11..7
vd/vs3
01000
6..0
opcode
0000111
Address and data pathaddr[i] = 0x8000 + i * 16
i=0
i=1
i=2
i=3
i=4
i=5
i=6
i=7
i=8
i=9
i=10
i=11
i=12
i=13
i=14
i=15
addr
0x8000
0x8010
0x8020
0x8030
0x8040
0x8050
0x8060
0x8070
0x8080
0x8090
0x80a0
0x80b0
0x80c0
0x80d0
0x80e0
0x80f0
mem
0x03
0x06
0x09
0x0c
0x0f
0x12
0x15
0x18
0x1b
0x1e
0x21
0x24
0x27
0x2a
0x2d
0x30
active
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
v8
...
...
-
...
...
...
...
-
...
...
...
...
-
...
...
...
Step 1 / 22
Show vector memory instruction encoding
The animation starts from the 32-bit vector memory encoding and shows the official bit fields: nf, mew, mop, vm, rs2/vs2 or lumop/sumop, width, register fields, and opcode.
Quick Understanding & Search Notes
VLSE8.V is an RVV 8-bit strided vector load: each active element uses memory address x[rs1] plus the lane index times x[rs2], where x[rs2] is a byte stride. vl and the v0.t mask decide which body elements participate in memory access.
The mnemonic fixes memory element width EEW=8; stride comes from integer register x[rs2], is measured in bytes, and is not implicitly scaled by EEW.
Strided access uses one scalar stride to generate the address sequence; indexed gather/scatter uses other families such as vluxei/vloxei or vsuxei/vsoxei.
x[rs2] may represent positive, negative, or zero stride; when the encoded rs2 field is x0, x0 is always 0 and the ISA permits implementations to perform fewer than one memory operation per active element for this zero-stride form.
With vm=0, v0.t selects participating body elements; with vm=1, all body elements participate. Masked-off elements do not perform memory accesses.
Loads update only active destination elements; inactive and tail destination elements follow the current vtype mask/tail policies.
V 1.0: RV32/RV64, valid vtype, enabled VS; EMUL=1/8..8 and legal group starts. Only active vstart≤i<vl elements access memory. VL=0 leaves destinations unchanged; normal completion resets vstart=0, preserving vl. Misalignment may succeed or trap.
Vector Execution Context
Syntax: vlse8.v vd, (rs1), rs2[, v0.t]; omitted v0.t gives vm=1, included gives vm=0. vd is a vector group, rs1 an integer base register, with base 0 for x0. 32-bit LOAD-FP: opcode=0000111, nf=000, mew=0, mop=10, width=000.
Data EEW=8, EMUL=(8/SEW)×LMUL. rs2 selects an integer register; address=x[rs1]+i×x[rs2]. The byte stride may be positive, negative, or zero, without scaling by 1.
The data width must be supported, EMUL in 1/8..8, and group starts legal. rs2=x0 permits fewer accesses than active elements; rs2≠x0 with value 0 requires one access per active element.
V 1.0 supports RV32/RV64; require valid vtype and enabled VS. Only elements with vstart≤i<vl and enabled masks access memory; masked vd cannot overlap v0. Prestart stays unchanged, inactive/tail follow vma/vta, and agnostic elements may retain old values or become all ones.
These strided and unordered indexed forms do not guarantee element access order. Misalignment may succeed or raise an address-misaligned exception; addresses must also satisfy access permissions. VL=0 or vstart≥vl updates no destination; normal completion resets vstart=0 and leaves vl unchanged.
Common Usage Scenarios
Structure field access
Assume enabled V/VS, supported widths, VLEN≥128, x10=0x8000, x11=4, and successful memory accesses; vsetvli gives vl=4, vstart=0, ta/ma. e8,m1; x5=4; v0.mask=[1,0,1,1]; addresses=[0x8000,0x8004,0x8008,0x800c]; active reads (i=0,2,3)=[10,30,40] → v8=[10,agnostic,30,40]. Disabled elements make no memory access. Agnostic elements may retain old values or become all ones; tails are not guaranteed zero. The address list is not an access-order guarantee.
Matrix row or column stride access
Assume enabled V/VS, supported widths, VLEN≥128, x10=0x8000, x11=4, and successful memory accesses; vsetvli gives vl=4, vstart=0, ta/ma. e8,m1; x5=4; v0.mask=[1,0,1,1]; addresses=[0x8000,0x8004,0x8008,0x800c]; active reads (i=0,2,3)=[10,30,40] → v8=[10,agnostic,30,40]. Disabled elements make no memory access. Agnostic elements may retain old values or become all ones; tails are not guaranteed zero. The address list is not an access-order guarantee.
Non-contiguous vector reads
Assume enabled V/VS, supported widths, VLEN≥128, x10=0x8000, x11=4, and successful memory accesses; vsetvli gives vl=4, vstart=0, ta/ma. e8,m1; x5=4; v0.mask=[1,0,1,1]; addresses=[0x8000,0x8004,0x8008,0x800c]; active reads (i=0,2,3)=[10,30,40] → v8=[10,agnostic,30,40]. Disabled elements make no memory access. Agnostic elements may retain old values or become all ones; tails are not guaranteed zero. The address list is not an access-order guarantee.
Pre-Use Checklist
Syntax Check
- Syntax: vlse8.v vd, (rs1), rs2[, v0.t]; omitted v0.t gives vm=1, included gives vm=0. vd is a vector group, rs1 an integer base register, with base 0 for x0. 32-bit LOAD-FP: opcode=0000111, nf=000, mew=0, mop=10, width=000.
- Data EEW=8, EMUL=(8/SEW)×LMUL. rs2 selects an integer register; address=x[rs1]+i×x[rs2]. The byte stride may be positive, negative, or zero, without scaling by 1.
Semantic Check
- The data width must be supported, EMUL in 1/8..8, and group starts legal. rs2=x0 permits fewer accesses than active elements; rs2≠x0 with value 0 requires one access per active element.
- V 1.0 supports RV32/RV64; require valid vtype and enabled VS. Only elements with vstart≤i<vl and enabled masks access memory; masked vd cannot overlap v0. Prestart stays unchanged, inactive/tail follow vma/vta, and agnostic elements may retain old values or become all ones.
- These strided and unordered indexed forms do not guarantee element access order. Misalignment may succeed or raise an address-misaligned exception; addresses must also satisfy access permissions. VL=0 or vstart≥vl updates no destination; normal completion resets vstart=0 and leaves vl unchanged.
Pitfalls / Common Confusions
The 8 in the mnemonic is memory element width EEW; the address increment comes from byte-count x[rs2] and is not implicitly scaled again by 1.
The stride may be positive, negative, or zero; rs2=x0 is the official zero-stride encoding, x0 is always 0, and implementations may perform fewer than one memory operation per active element for that form.
Masked-off elements do not perform memory reads, and destination elements follow the current mask policy.
Do not rely on element access order to express side-effecting memory or overlapping-address semantics.
FAQ
How is VLSE8.V different from unit-stride VLE8.V?
Unit-stride access advances by consecutive 1-byte elements; VLSE8.V uses byte stride x[rs2], so it can access structure fields, matrix columns, or reverse sequences.
Is rs2=x0 different from x[rs2]=0 for VLSE8.V?
Yes. rs2=x0 directly encodes the x0 zero-stride form; the ISA permits implementations to perform fewer than one memory operation per active element for that form. If rs2 is not x0 but its register value is 0, the ordinary strided-access semantics still apply.
Do elements disabled by v0.t access memory?
No. With vm=0, a body element whose v0.t bit is 0 does not perform that element's load memory access.