VLUXEI8.V

RISC-V VLUXEI8.V Instruction Details

Q: What unit is used for VLUXEI8.V address offsets?

Indexed-load vs2 elements are unsigned byte offsets.

Q: How does VLUXEI8.V handle masking?

With vm=0, v0 selects active elements; with vm=1, all body elements participate. Inactive and tail elements follow the current policies.

Instruction ManualV-type

Use x[rs1] plus 8-bit unsigned byte offsets from vs2 for unordered indexed loads.

Instruction Syntax

vluxei8.v vd, (rs1), vs2, vm

Operand Breakdown

32-bit LOAD-FP: opcode=0000111, nf=000, mew=0, mop=01, width=000. vd is the data destination group, rs1 the integer base, and vs2 unsigned byte offsets, without implicit scaling.

Data EEW=SEW, EMUL=LMUL; index EEW=8, EMUL=(EEW/SEW)×LMUL, in 1/8..8 with legal group starts. Zero-extend indices to XLEN before adding x[rs1]. rs1=x0 gives base 0.

Omitting v0.t gives vm=1; including it gives vm=0. Masked vd cannot overlap v0; one register cannot be read as both an EEW=1 mask and different-EEW data. Different-EEW destination/source overlap must satisfy the low/high-end rules; legal overlap forces ma/ta.

Require V 1.0, enabled VS, valid vtype, and supported widths. Prestart stays unchanged; body is vstart≤i<vl. VL=0 or vstart≥vl updates no destination, including tails; normal completion resets vstart=0 and leaves vl unchanged.

Only active elements access memory, without element-order guarantees. Misalignment may succeed or raise an address-misaligned exception; access permissions still apply. Inactive/tail elements follow vma/vta and may retain old values or become all ones.

VVector MemoryIndexed Vector Load

Related Search Terms

VLUXEI8.V instruction RISC-V VLUXEI8.V vluxei8.v syntax vluxei8.v encoding RVV indexed load ei8 index unordered indexed load

Instruction Behavior

VLUXEI8.V is an RISC-V V-extension unordered indexed vector load instruction. Each active element forms its address as x[rs1] + zero_extend(vs2[i]); ei8 is the index EEW, so the index is an unsigned byte offset, not an element number. The unordered form does not guarantee observation in element-number order. With vm=0, elements disabled by v0.t do not access memory.

VLUXEI8.V Decode And Execute Animation

Decode the 8-bit indexed load, then compute each element address as x[rs1] + zero_extend(vs2[i]).

Instruction input

vluxei8.v

vdVector register v0-v31rs1Integer base-address registervs2Index vector register v0-v31vmexecution mask control

VLSEWx[rs1]vs2 index bytes (8)0..0xff, unsigned byte offsetsmemory elements0..0xffffffff, comma-separatedv0 mask bits0/1 only, length equals VL

Execution context: index EEW=8, data SEW=32, index EEW=8 is narrower than XLEN=64, so it is zero-extended before addition, unordered indexed accesses do not guarantee element order, LMUL=m1, vstart=0 (a nonzero value starts at that element). These are not assembly syntax operands.

Teaching context: XLEN=64, VLEN=4096, SEW=32, LMUL=m1, VLMAX=128, index EMUL=0.25, valid vtype, enabled VS, vstart=0, and ta/ma. All selected accesses are assumed successful; traps are not modeled. Unaligned accesses apply only where the environment supports them. rs1=x0 fixes the base at 0. The memory elements input gives the value observed by each active read, allowing memory to change between accesses; it is not a static byte-memory image. Per-element steps do not represent processor cycles or actual access order; unordered indexed accesses do not guarantee element order. Inactive/tail “-” means the result is not shown and may retain the old value or become all ones. VL=0 leaves the destination unchanged; normal completion resets vstart=0.

Encoding fieldsvluxei8.v / LOAD-FP

31..29

000

mew

27..26

mop

24..20

vs2

10000

19..15

rs1

01010

14..12

width

000

11..7

vd/vs3

01000

6..0

opcode

0000111

Address and data pathaddr[i] = 0x8000 + zero_extend(vs2[i])

i=0

i=1

i=2

i=3

i=4

i=5

i=6

i=7

i=8

i=9

i=10

i=11

i=12

i=13

i=14

i=15

vs2 byte offset

0x01

0x04

0x07

0x0a

0x0d

0x10

0x13

0x16

0x19

0x1c

0x1f

0x22

0x25

0x28

0x2b

0x2e

addr

0x8001

0x8004

0x8007

0x800a

0x800d

0x8010

0x8013

0x8016

0x8019

0x801c

0x801f

0x8022

0x8025

0x8028

0x802b

0x802e

mem

0x00000101

0x00000202

0x00000303

0x00000404

0x00000505

0x00000606

0x00000707

0x00000808

0x00000909

0x00000a0a

0x00000b0b

0x00000c0c

0x00000d0d

0x00000e0e

0x00000f0f

0x00001010

active

...

Step 1 / 22

Show vector memory instruction encoding

The animation starts from the 32-bit vector memory encoding and shows the official bit fields: nf, mew, mop, vm, rs2/vs2 or lumop/sumop, width, register fields, and opcode.

Quick Understanding & Search Notes

VLUXEI8.V uses vs2 as byte offsets, not element numbers; the unordered form must not be used when element access order is required.

Index EEW=8; loaded data elements use the current SEW, and register-group use is constrained by data SEW/LMUL together with index EEW.

Unordered indexed loads allow accesses to be observed out of element order; offsets are unsigned byte offsets.

vm=0 uses v0 as the execution mask and vm=1 is unmasked; inactive and tail elements follow the current vma/vta policy.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, V 1.0

Vector Execution Context

32-bit LOAD-FP: opcode=0000111, nf=000, mew=0, mop=01, width=000. vd is the data destination group, rs1 the integer base, and vs2 unsigned byte offsets, without implicit scaling.

Data EEW=SEW, EMUL=LMUL; index EEW=8, EMUL=(EEW/SEW)×LMUL, in 1/8..8 with legal group starts. Zero-extend indices to XLEN before adding x[rs1]. rs1=x0 gives base 0.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, Chapter 31

Common Usage Scenarios

Gather using unsigned byte offsets

Assume RV32/RV64 V; enabled VS, valid vtype, VLEN≥128, and supported widths; vsetvli gives vl=4, vstart=0, ta/ma, unmasked. x10=0x8000, x11=4; e32,m1; v2 byte offsets=[0,8,16,24]; addresses=[0x8000,0x8008,0x8010,0x8018]; observed memory=[10,20,30,40] → v1=[10,20,30,40]. All accesses succeed; the address list is not an access-order guarantee. Tails are not guaranteed zero; normal completion resets vstart=0.

Indexed reads without element-order guarantees

Pre-Use Checklist

Syntax Check

32-bit LOAD-FP: opcode=0000111, nf=000, mew=0, mop=01, width=000. vd is the data destination group, rs1 the integer base, and vs2 unsigned byte offsets, without implicit scaling.
Data EEW=SEW, EMUL=LMUL; index EEW=8, EMUL=(EEW/SEW)×LMUL, in 1/8..8 with legal group starts. Zero-extend indices to XLEN before adding x[rs1]. rs1=x0 gives base 0.

Semantic Check

Omitting v0.t gives vm=1; including it gives vm=0. Masked vd cannot overlap v0; one register cannot be read as both an EEW=1 mask and different-EEW data. Different-EEW destination/source overlap must satisfy the low/high-end rules; legal overlap forces ma/ta.
Require V 1.0, enabled VS, valid vtype, and supported widths. Prestart stays unchanged; body is vstart≤i<vl. VL=0 or vstart≥vl updates no destination, including tails; normal completion resets vstart=0 and leaves vl unchanged.
Only active elements access memory, without element-order guarantees. Misalignment may succeed or raise an address-misaligned exception; access permissions still apply. Inactive/tail elements follow vma/vta and may retain old values or become all ones.

Pitfalls / Common Confusions

ei8 is the index EEW, not the SEW of the loaded data; data element width still comes from current vtype.

vs2[i] is an unsigned byte offset; the address is x[rs1] + zero_extend(vs2[i]), not x[rs1] + i * EEW and not an element number.

Unordered indexed loads do not guarantee element access order; use the ordered indexed form when an address space requires element order.

With vm=0, elements disabled by v0.t perform no memory read and must not be shown as writing zero.

FAQ

What unit is used for VLUXEI8.V address offsets?