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VLUXEI32.V

RISC-V VLUXEI32.V Instruction Details

Instruction ManualR-type

Use x[rs1] plus 32-bit unsigned byte offsets in vs2 for unordered indexed loads.

Instruction Syntax

vluxei32.v vd, (rs1), vs2, vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
VVector LoadIndexed Access
Related Search Terms
VLUXEI32.V instructionRISC-V VLUXEI32.Vvluxei32.v syntaxvluxei32.v RVVvluxei32 32-bit indexunordered indexed load

Instruction Behavior

VLUXEI32.V is a RISC-V V unordered indexed vector load instruction with 32-bit index EEW. Each active element address is x[rs1] plus a 32-bit unsigned byte offset from vs2; the unordered form does not guarantee element-order observation. It operates on active elements within vl, with masking and tail behavior following RVV rules.

Quick Understanding & Search Notes

VLUXEI32.V uses vs2 as byte offsets, not element numbers; the unordered form must not be used when element access order is required.

Index EEW=32; loaded data elements use the current SEW, and register-group use is constrained by data SEW/LMUL together with index EEW.
Unordered indexed loads allow accesses to be observed out of element order; offsets are unsigned byte offsets.
vm=0 uses v0 as the execution mask and vm=1 is unmasked; inactive and tail elements follow the current vma/vta policy.
RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations

Common Usage Scenarios

Sparse Access

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vluxei32.v v1, (a0), v2».

Unordered Indirect Load

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vluxei32.v v1, (a0), v2».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

The index width is fixed at 32 bits and is independent of data SEW; vs2 supplies unsigned byte offsets, not element numbers.
The unordered form does not guarantee element memory-access order; use ordered indexed loads for I/O addresses that require ordering.

FAQ

What unit is used for VLUXEI32.V address offsets?

Indexed-load vs2 elements are unsigned byte offsets.

How does VLUXEI32.V handle masking?

With vm=0, v0 selects active elements; with vm=1, all body elements participate. Inactive and tail elements follow the current policies.