What unit is used for VLUXEI32.V address offsets?
Indexed-load vs2 elements are unsigned byte offsets.
VLUXEI32.V
RISC-V VLUXEI32.V Instruction Details
Instruction ManualV-typeUse x[rs1] plus 32-bit unsigned byte offsets from vs2 for unordered indexed loads.
Instruction Syntax
vluxei32.v vd, (rs1), vs2, vm
Operand Breakdown
Syntax: vluxei32.v vd, (rs1), vs2[, v0.t]; omitted v0.t gives vm=1, included gives vm=0. vd is a vector group, rs1 an integer base register, with base 0 for x0. 32-bit LOAD-FP: opcode=0000111, nf=000, mew=0, mop=01, width=110.
ei32 is index EEW, not data width. Data EEW=SEW and EMUL=LMUL; index EMUL=(32/SEW)×LMUL. Offsets count bytes without implicit scaling; narrower-than-XLEN offsets are zero-extended, while equal-width offsets are added directly.
The index width must be supported, EMUL in 1/8..8, and group starts legal. Different-EEW overlap must satisfy low/high-end restrictions; legal different-width overlap forces ma/ta. A register cannot be read as both an EEW=1 mask and a different-EEW index source.
V 1.0 supports RV32/RV64; require valid vtype and enabled VS. Only elements with vstart≤i<vl and enabled masks access memory; masked vd cannot overlap v0. Prestart stays unchanged, inactive/tail follow vma/vta, and agnostic elements may retain old values or become all ones.
These strided and unordered indexed forms do not guarantee element access order. Misalignment may succeed or raise an address-misaligned exception; addresses must also satisfy access permissions. VL=0 or vstart≥vl updates no destination; normal completion resets vstart=0 and leaves vl unchanged.
VVector MemoryIndexed Vector Load
Instruction Behavior
VLUXEI32.V is a RISC-V V-extension unordered indexed vector load instruction. Each active element forms its address as x[rs1] + zero_extend(vs2[i]); ei32 is the index EEW, so the index is an unsigned byte offset, not an element number. The unordered form does not guarantee observation in element-number order. With vm=0, elements disabled by v0.t do not access memory.
VLUXEI32.V Decode And Execute Animation
Decode the 32-bit indexed load, then compute each element address as x[rs1] + zero_extend(vs2[i]).
Instruction input
vluxei32.v
Execution context: index EEW=32, data SEW=32, index EEW=32 is narrower than XLEN=64, so it is zero-extended before addition, unordered indexed accesses do not guarantee element order, LMUL=m1, vstart=0 (a nonzero value starts at that element). These are not assembly syntax operands.
Teaching context: XLEN=64, VLEN=4096, SEW=32, LMUL=m1, VLMAX=128, index EMUL=1, valid vtype, enabled VS, vstart=0, and ta/ma. All selected accesses are assumed successful; traps are not modeled. Unaligned accesses apply only where the environment supports them. rs1=x0 fixes the base at 0. The memory elements input gives the value observed by each active read, allowing memory to change between accesses; it is not a static byte-memory image. Per-element steps do not represent processor cycles or actual access order; unordered indexed accesses do not guarantee element order. Inactive/tail “-” means the result is not shown and may retain the old value or become all ones. VL=0 leaves the destination unchanged; normal completion resets vstart=0.
Encoding fieldsvluxei32.v / LOAD-FP
31..29
nf
000
28
mew
0
27..26
mop
01
25
vm
0
24..20
vs2
10000
19..15
rs1
01010
14..12
width
110
11..7
vd/vs3
01000
6..0
opcode
0000111
Address and data pathaddr[i] = 0x8000 + zero_extend(vs2[i])
i=0
i=1
i=2
i=3
i=4
i=5
i=6
i=7
i=8
i=9
i=10
i=11
i=12
i=13
i=14
i=15
vs2 byte offset
0x00000001
0x00000004
0x00000007
0x0000000a
0x0000000d
0x00000010
0x00000013
0x00000016
0x00000019
0x0000001c
0x0000001f
0x00000022
0x00000025
0x00000028
0x0000002b
0x0000002e
addr
0x8001
0x8004
0x8007
0x800a
0x800d
0x8010
0x8013
0x8016
0x8019
0x801c
0x801f
0x8022
0x8025
0x8028
0x802b
0x802e
mem
0x00000101
0x00000202
0x00000303
0x00000404
0x00000505
0x00000606
0x00000707
0x00000808
0x00000909
0x00000a0a
0x00000b0b
0x00000c0c
0x00000d0d
0x00000e0e
0x00000f0f
0x00001010
active
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
v8
...
...
-
...
...
...
...
-
...
...
...
...
-
...
...
...
Step 1 / 22
Show vector memory instruction encoding
The animation starts from the 32-bit vector memory encoding and shows the official bit fields: nf, mew, mop, vm, rs2/vs2 or lumop/sumop, width, register fields, and opcode.
Quick Understanding & Search Notes
VLUXEI32.V uses vs2 as byte offsets, not element numbers; the unordered form must not be used when element access order is required.
Index EEW=32; loaded data elements use the current SEW, and register-group use is constrained by data SEW/LMUL together with index EEW.
Unordered indexed loads allow accesses to be observed out of element order; offsets are unsigned byte offsets.
vm=0 uses v0 as the execution mask and vm=1 is unmasked; inactive and tail elements follow the current vma/vta policy.
V 1.0: RV32/RV64, valid vtype, enabled VS; EMUL=1/8..8 and legal group starts. Only active vstart≤i<vl elements access memory. VL=0 leaves destinations unchanged; normal completion resets vstart=0, preserving vl. Misalignment may succeed or trap.
Vector Execution Context
Syntax: vluxei32.v vd, (rs1), vs2[, v0.t]; omitted v0.t gives vm=1, included gives vm=0. vd is a vector group, rs1 an integer base register, with base 0 for x0. 32-bit LOAD-FP: opcode=0000111, nf=000, mew=0, mop=01, width=110.
ei32 is index EEW, not data width. Data EEW=SEW and EMUL=LMUL; index EMUL=(32/SEW)×LMUL. Offsets count bytes without implicit scaling; narrower-than-XLEN offsets are zero-extended, while equal-width offsets are added directly.
The index width must be supported, EMUL in 1/8..8, and group starts legal. Different-EEW overlap must satisfy low/high-end restrictions; legal different-width overlap forces ma/ta. A register cannot be read as both an EEW=1 mask and a different-EEW index source.
V 1.0 supports RV32/RV64; require valid vtype and enabled VS. Only elements with vstart≤i<vl and enabled masks access memory; masked vd cannot overlap v0. Prestart stays unchanged, inactive/tail follow vma/vta, and agnostic elements may retain old values or become all ones.
These strided and unordered indexed forms do not guarantee element access order. Misalignment may succeed or raise an address-misaligned exception; addresses must also satisfy access permissions. VL=0 or vstart≥vl updates no destination; normal completion resets vstart=0 and leaves vl unchanged.
Common Usage Scenarios
Sparse data reads
Assume enabled V/VS, supported widths, VLEN≥128, x10=0x8000, x11=4, and successful memory accesses; vsetvli gives vl=4, vstart=0, ta/ma. e32,m1; v2 byte offsets=[0,8,16,24]; addresses=[0x8000,0x8008,0x8010,0x8018]; memory values=[10,20,30,40] → v1=[10,20,30,40]. Omitting v0.t makes this unmasked. Agnostic elements may retain old values or become all ones; tails are not guaranteed zero. The address list is not an access-order guarantee.
Gather access without ordering needs
Assume enabled V/VS, supported widths, VLEN≥128, x10=0x8000, x11=4, and successful memory accesses; vsetvli gives vl=4, vstart=0, ta/ma. e32,m1; v2 byte offsets=[0,8,16,24]; addresses=[0x8000,0x8008,0x8010,0x8018]; memory values=[10,20,30,40] → v1=[10,20,30,40]. Omitting v0.t makes this unmasked. Agnostic elements may retain old values or become all ones; tails are not guaranteed zero. The address list is not an access-order guarantee.
Indirect array loads
Assume enabled V/VS, supported widths, VLEN≥128, x10=0x8000, x11=4, and successful memory accesses; vsetvli gives vl=4, vstart=0, ta/ma. e32,m1; v2 byte offsets=[0,8,16,24]; addresses=[0x8000,0x8008,0x8010,0x8018]; memory values=[10,20,30,40] → v1=[10,20,30,40]. Omitting v0.t makes this unmasked. Agnostic elements may retain old values or become all ones; tails are not guaranteed zero. The address list is not an access-order guarantee.
Pre-Use Checklist
Syntax Check
- Syntax: vluxei32.v vd, (rs1), vs2[, v0.t]; omitted v0.t gives vm=1, included gives vm=0. vd is a vector group, rs1 an integer base register, with base 0 for x0. 32-bit LOAD-FP: opcode=0000111, nf=000, mew=0, mop=01, width=110.
- ei32 is index EEW, not data width. Data EEW=SEW and EMUL=LMUL; index EMUL=(32/SEW)×LMUL. Offsets count bytes without implicit scaling; narrower-than-XLEN offsets are zero-extended, while equal-width offsets are added directly.
Semantic Check
- The index width must be supported, EMUL in 1/8..8, and group starts legal. Different-EEW overlap must satisfy low/high-end restrictions; legal different-width overlap forces ma/ta. A register cannot be read as both an EEW=1 mask and a different-EEW index source.
- V 1.0 supports RV32/RV64; require valid vtype and enabled VS. Only elements with vstart≤i<vl and enabled masks access memory; masked vd cannot overlap v0. Prestart stays unchanged, inactive/tail follow vma/vta, and agnostic elements may retain old values or become all ones.
- These strided and unordered indexed forms do not guarantee element access order. Misalignment may succeed or raise an address-misaligned exception; addresses must also satisfy access permissions. VL=0 or vstart≥vl updates no destination; normal completion resets vstart=0 and leaves vl unchanged.
Pitfalls / Common Confusions
ei32 is the index EEW, not the SEW of the loaded data; data element width still comes from current vtype.
vs2[i] is an unsigned byte offset; the address is x[rs1] + zero_extend(vs2[i]), not x[rs1] + i * EEW and not an element number.
Unordered indexed loads do not guarantee element access order; use the ordered indexed form when an address space requires element order.
With vm=0, elements disabled by v0.t perform no memory read and must not be shown as writing zero.
FAQ
How does VLUXEI32.V handle masking?
With vm=0, v0 selects active elements; with vm=1, all body elements participate. Inactive and tail elements follow the current policies.