What unit does VLSE16.V use for stride?
The stride is the byte count in x[rs2]. It is not an element count and is not implicitly multiplied by EEW again; if encoded as rs2=x0, x0 is always 0.
VLSE16.V
RISC-V VLSE16.V Instruction Details
Instruction ManualV-typeLoad 16-bit vector elements into vd using byte stride x[rs2] from base x[rs1].
Instruction Syntax
vlse16.v vd, (rs1), rs2, vm
Operand Breakdown
Syntax: vlse16.v vd, (rs1), rs2[, v0.t]; omitted v0.t gives vm=1 and included v0.t gives vm=0. vd is a vector group, rs1 an integer base, with base 0 for rs1=x0.
Data EEW=16; EMUL=(16/SEW)×LMUL must be in 1/8..8 with legal group starts. rs2 selects an integer register containing a signed byte stride, without scaling by 2.
Address is x[rs1]+i×x[rs2]; negative/zero strides are supported and accesses are unordered. rs2=x0 permits fewer accesses than active elements; rs2≠x0 with value 0 requires one access per active element.
Require enabled V/VS and valid vtype. Only elements with vstart≤i<vl and enabled masks access memory; masked vd cannot overlap v0. Prestart stays unchanged, inactive/tail follow vma/vta, and legal different-EEW overlap forces ma/ta. VL=0 or vstart≥vl updates no destination; normal completion resets vstart=0 and leaves vl unchanged.
VVector MemoryVector Load
Instruction Behavior
VLSE16.V is a RISC-V V 16-bit strided vector load. Active body elements use address x[rs1] plus the lane index times x[rs2]; x[rs2] is a byte-count stride and may represent positive, negative, or zero stride. With vm=0, v0.t selects elements, and masked-off elements do not access memory.
VLSE16.V Decode And Execute Animation
Decode the 16-bit strided load, then compute each element address as x[rs1] + i * x[rs2] (16 bytes).
Instruction input
vlse16.v
Execution context: EEW=16, stride=x[rs2]=16 bytes, example SEW=16, LMUL=m1, vstart=0 (a nonzero value starts at that element). These are not assembly syntax operands.
Teaching context: XLEN=64, VLEN=4096, SEW=16, LMUL=m1, VLMAX=256, data EMUL=m1, valid vtype, enabled VS, vstart=0, and ta/ma. All selected accesses are assumed successful; traps are not modeled. Unaligned accesses apply only where the environment supports them. rs1=x0 fixes the base at 0. The memory elements input gives the value observed by each active read, allowing memory to change between accesses; it is not a static byte-memory image. The rs2=x0 example selects the permitted execution with one read per active element. Per-element steps do not represent processor cycles or actual access order; strided accesses are unordered. Inactive/tail “-” means the result is not shown and may retain the old value or become all ones. VL=0 leaves the destination unchanged; normal completion resets vstart=0.
Encoding fieldsvlse16.v / LOAD-FP
31..29
nf
000
28
mew
0
27..26
mop
10
25
vm
0
24..20
rs2
00101
19..15
rs1
01010
14..12
width
101
11..7
vd/vs3
01000
6..0
opcode
0000111
Address and data pathaddr[i] = 0x8000 + i * 16
i=0
i=1
i=2
i=3
i=4
i=5
i=6
i=7
i=8
i=9
i=10
i=11
i=12
i=13
i=14
i=15
addr
0x8000
0x8010
0x8020
0x8030
0x8040
0x8050
0x8060
0x8070
0x8080
0x8090
0x80a0
0x80b0
0x80c0
0x80d0
0x80e0
0x80f0
mem
0x0011
0x0022
0x0033
0x0044
0x0055
0x0066
0x0077
0x0088
0x0099
0x00aa
0x00bb
0x00cc
0x00dd
0x00ee
0x00ff
0x0110
active
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
v8
...
...
-
...
...
...
...
-
...
...
...
...
-
...
...
...
Step 1 / 22
Show vector memory instruction encoding
The animation starts from the 32-bit vector memory encoding and shows the official bit fields: nf, mew, mop, vm, rs2/vs2 or lumop/sumop, width, register fields, and opcode.
Quick Understanding & Search Notes
VLSE16.V is an RVV 16-bit strided vector load: each active element uses memory address x[rs1] plus the lane index times x[rs2], where x[rs2] is a byte stride. vl and the v0.t mask decide which body elements participate in memory access.
The mnemonic fixes memory element width EEW=16; stride comes from integer register x[rs2], is measured in bytes, and is not implicitly scaled by EEW.
Strided access uses one scalar stride to generate the address sequence; indexed gather/scatter uses other families such as vluxei/vloxei or vsuxei/vsoxei.
x[rs2] may represent positive, negative, or zero stride; when the encoded rs2 field is x0, x0 is always 0 and the ISA permits implementations to perform fewer than one memory operation per active element for this zero-stride form.
With vm=0, v0.t selects participating body elements; with vm=1, all body elements participate. Masked-off elements do not perform memory accesses.
Loads update only active destination elements; inactive and tail destination elements follow the current vtype mask/tail policies.
Vector Execution Context
Syntax: vlse16.v vd, (rs1), rs2[, v0.t]; omitted v0.t gives vm=1 and included v0.t gives vm=0. vd is a vector group, rs1 an integer base, with base 0 for rs1=x0.
Data EEW=16; EMUL=(16/SEW)×LMUL must be in 1/8..8 with legal group starts. rs2 selects an integer register containing a signed byte stride, without scaling by 2.
Address is x[rs1]+i×x[rs2]; negative/zero strides are supported and accesses are unordered. rs2=x0 permits fewer accesses than active elements; rs2≠x0 with value 0 requires one access per active element.
Require enabled V/VS and valid vtype. Only elements with vstart≤i<vl and enabled masks access memory; masked vd cannot overlap v0. Prestart stays unchanged, inactive/tail follow vma/vta, and legal different-EEW overlap forces ma/ta. VL=0 or vstart≥vl updates no destination; normal completion resets vstart=0 and leaves vl unchanged.
Common Usage Scenarios
Structure field access
Assume enabled V/VS, supported data/index widths, VLEN≥128, x10=0x8000, x11=4, and successful memory accesses; vsetvli sets vl=4, vstart=0, ta/ma. e16,m1; x5=8; v0.mask=[1,0,1,1]; addresses=[0x8000,0x8008,0x8010,0x8018]; active reads (i=0,2,3)=[10,30,40] → v8=[10,agnostic,30,40]. Disabled elements make no memory read. Agnostic elements may retain old values or become all ones; tails are not guaranteed zero.
Matrix row or column stride access
Assume enabled V/VS, supported data/index widths, VLEN≥128, x10=0x8000, x11=4, and successful memory accesses; vsetvli sets vl=4, vstart=0, ta/ma. e16,m1; x5=8; v0.mask=[1,0,1,1]; addresses=[0x8000,0x8008,0x8010,0x8018]; active reads (i=0,2,3)=[10,30,40] → v8=[10,agnostic,30,40]. Disabled elements make no memory read. Agnostic elements may retain old values or become all ones; tails are not guaranteed zero.
Non-contiguous vector reads
Assume enabled V/VS, supported data/index widths, VLEN≥128, x10=0x8000, x11=4, and successful memory accesses; vsetvli sets vl=4, vstart=0, ta/ma. e16,m1; x5=8; v0.mask=[1,0,1,1]; addresses=[0x8000,0x8008,0x8010,0x8018]; active reads (i=0,2,3)=[10,30,40] → v8=[10,agnostic,30,40]. Disabled elements make no memory read. Agnostic elements may retain old values or become all ones; tails are not guaranteed zero.
Pre-Use Checklist
Syntax Check
- Syntax: vlse16.v vd, (rs1), rs2[, v0.t]; omitted v0.t gives vm=1 and included v0.t gives vm=0. vd is a vector group, rs1 an integer base, with base 0 for rs1=x0.
- Data EEW=16; EMUL=(16/SEW)×LMUL must be in 1/8..8 with legal group starts. rs2 selects an integer register containing a signed byte stride, without scaling by 2.
Semantic Check
- Address is x[rs1]+i×x[rs2]; negative/zero strides are supported and accesses are unordered. rs2=x0 permits fewer accesses than active elements; rs2≠x0 with value 0 requires one access per active element.
- Require enabled V/VS and valid vtype. Only elements with vstart≤i<vl and enabled masks access memory; masked vd cannot overlap v0. Prestart stays unchanged, inactive/tail follow vma/vta, and legal different-EEW overlap forces ma/ta. VL=0 or vstart≥vl updates no destination; normal completion resets vstart=0 and leaves vl unchanged.
Pitfalls / Common Confusions
The 16 in the mnemonic is memory element width EEW; the address increment comes from byte-count x[rs2] and is not implicitly scaled again by 2.
The stride may be positive, negative, or zero; rs2=x0 is the official zero-stride encoding, x0 is always 0, and implementations may perform fewer than one memory operation per active element for that form.
Masked-off elements do not perform memory reads, and destination elements follow the current mask policy.
Do not rely on element access order to express side-effecting memory or overlapping-address semantics.
An unaligned 16-bit vector element access may transfer successfully or raise an address-misaligned exception on that element; vector and scalar misalignment support are independent.
FAQ
How is VLSE16.V different from unit-stride VLE16.V?
Unit-stride access advances by consecutive 2-byte elements; VLSE16.V uses byte stride x[rs2], so it can access structure fields, matrix columns, or reverse sequences.
Is rs2=x0 different from x[rs2]=0 for VLSE16.V?
Yes. rs2=x0 directly encodes the x0 zero-stride form; the ISA permits implementations to perform fewer than one memory operation per active element for that form. If rs2 is not x0 but its register value is 0, the ordinary strided-access semantics still apply.
Do elements disabled by v0.t access memory?
No. With vm=0, a body element whose v0.t bit is 0 does not perform that element's load memory access.