VSSE16.V

RISC-V VSSE16.V Instruction Details

Instruction ManualV-type

Store 16-bit vector elements from vs3 using byte stride x[rs2] from base x[rs1].

Instruction Syntax

vsse16.v vs3, (rs1), rs2, vm

Operand Breakdown

vs3 supplies store data, rs1 the base and rs2 the byte stride; x0 supplies zero. Fixed EEW=16; EMUL=(EEW/SEW)*LMUL must be 1/8..8 with aligned groups. SEW need not equal EEW.

32-bit STORE-FP: opcode=0100111, nf=000, mew=0, mop=10, width=101; vm at bit25, rs2 at bits24:20, rs1 at bits19:15, vs3 at bits11:7. vm=0 uses v0.t; omission means vm=1.

Active addresses are x[rs1]+i*x[rs2], without EEW scaling; positive, negative and zero strides are supported. rs2=x0 permits fewer than one access per active element; a non-x0 register containing zero still requires one access per active element. Strided accesses are unordered, with no guaranteed final value at overlapping addresses.

Require V 1.0, enabled vector state, vill=0 and supported vtype/EEW. v0 cannot supply both EEW=1 mask and data. Only mask-enabled vstart<=i<vl elements access memory; inactive/tail and vstart>=vl (including vl=0) make no access. Misalignment may succeed or fault, and active accesses may trap. Sources stay unchanged; normal completion resets vstart=0.

VVector MemoryVector Store

Related Search Terms

VSSE16.V instruction RISC-V VSSE16.V vsse16.v syntax vsse16.v encoding RVV strided store 16-bit vector store vsse16.v byte stride

Instruction Behavior

VSSE16.V is a RISC-V V 16-bit strided vector store. Active body elements use address x[rs1] plus the lane index times x[rs2]; x[rs2] is a byte-count stride and may represent positive, negative, or zero stride. With vm=0, v0.t selects elements, and masked-off elements do not access memory.

VSSE16.V Decode And Execute Animation

Decode the 16-bit strided store, then compute each element address as x[rs1] + i * x[rs2] (16 bytes).

Instruction input

vsse16.v

vs3Vector register v0-v31rs1Integer base-address registerrs2Integer stride registervmexecution mask control

VLx[rs1]x[rs2] stride bytesTeaching range, not an ISA limit: -32768..32768 bytes, including negative and zerovs3 elements0..0xffff, comma-separatedv0 mask bits0/1 only, length equals VL

Execution context: EEW=16, stride=x[rs2]=16 bytes, example SEW=16, LMUL=m1, vstart=0 (a nonzero value starts at that element). These are not assembly syntax operands.

Teaching context: V 1.0, enabled vector state, valid supported vtype; fix XLEN=64, VLEN=4096, SEW=EEW=16, LMUL=EMUL=m1, vstart=0, VLMAX=256. rs1=x0 supplies base zero; equal rs1/rs2 require equal values. v0 cannot supply both the EEW=1 mask and data. Active writes are assumed successful; misaligned accesses require environment support, and traps are not modeled. Rows show per-element store events, not a final byte-memory image; accesses are unordered, and overlapping addresses have no guaranteed final value. rs2=x0 shows only candidate accesses that may be combined; non-x0 zero stride still requires one access per active element. VL=0, inactive elements and tails make no access. Sources stay unchanged; normal completion resets vstart=0. Stages are teaching steps, not processor cycles.

Encoding fieldsvsse16.v / STORE-FP

31..29

000

mew

27..26

mop

24..20

rs2

00101

19..15

rs1

01010

14..12

width

101

11..7

vd/vs3

01000

6..0

opcode

0100111

Address and data pathaddr[i] = 0x8000 + i * 16

i=0

i=1

i=2

i=3

i=4

i=5

i=6

i=7

i=8

i=9

i=10

i=11

i=12

i=13

i=14

i=15

addr

0x8000

0x8010

0x8020

0x8030

0x8040

0x8050

0x8060

0x8070

0x8080

0x8090

0x80a0

0x80b0

0x80c0

0x80d0

0x80e0

0x80f0

0x0011

0x0022

0x0033

0x0044

0x0055

0x0066

0x0077

0x0088

0x0099

0x00aa

0x00bb

0x00cc

0x00dd

0x00ee

0x00ff

0x0110

active

memory write

...

Step 1 / 22

Show vector memory instruction encoding

The animation starts from the 32-bit vector memory encoding and shows the official bit fields: nf, mew, mop, vm, rs2/vs2 or lumop/sumop, width, register fields, and opcode.

Quick Understanding & Search Notes

VSSE16.V is an RVV 16-bit strided vector store: each active element uses memory address x[rs1] plus the lane index times x[rs2], where x[rs2] is a byte stride. vl and the v0.t mask decide which body elements participate in memory access.

The mnemonic fixes memory element width EEW=16; stride comes from integer register x[rs2], is measured in bytes, and is not implicitly scaled by EEW.

Strided access uses one scalar stride to generate the address sequence; indexed gather/scatter uses other families such as vluxei/vloxei or vsuxei/vsoxei.

x[rs2] may represent positive, negative, or zero stride; when the encoded rs2 field is x0, x0 is always 0 and the ISA permits implementations to perform fewer than one memory operation per active element for this zero-stride form.

With vm=0, v0.t selects participating body elements; with vm=1, all body elements participate. Masked-off elements do not perform memory accesses.

Stores produce memory writes only for active elements; inactive and tail elements do not perform that element store access.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, Chapter 31, “V” Standard Extension for Vector Operations, Version 1.0

Vector Execution Context

vs3 supplies store data, rs1 the base and rs2 the byte stride; x0 supplies zero. Fixed EEW=16; EMUL=(EEW/SEW)*LMUL must be 1/8..8 with aligned groups. SEW need not equal EEW.

32-bit STORE-FP: opcode=0100111, nf=000, mew=0, mop=10, width=101; vm at bit25, rs2 at bits24:20, rs1 at bits19:15, vs3 at bits11:7. vm=0 uses v0.t; omission means vm=1.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, Chapter 31

Common Usage Scenarios

Structure field access

Assume enabled V/VS, valid e16,m1,ta,ma, VLEN=4096, XLEN=64, a0=0x8000, a2=4, v8=[10,20,30,40], v0.mask[0..3]=1011, writable memory and successful accesses. vsetvli sets vl=4 and vstart=0; li sets t0=8 bytes. Active elements 0,2,3 store [10,30,40] at [0x8000,0x8010,0x8018]. Element 1 and tails make no access; sources stay unchanged. The address list does not specify access order; normal completion resets vstart=0.

Matrix row or column stride access

Non-contiguous vector writes

Pre-Use Checklist

Syntax Check

vs3 supplies store data, rs1 the base and rs2 the byte stride; x0 supplies zero. Fixed EEW=16; EMUL=(EEW/SEW)*LMUL must be 1/8..8 with aligned groups. SEW need not equal EEW.
32-bit STORE-FP: opcode=0100111, nf=000, mew=0, mop=10, width=101; vm at bit25, rs2 at bits24:20, rs1 at bits19:15, vs3 at bits11:7. vm=0 uses v0.t; omission means vm=1.

Semantic Check

Active addresses are x[rs1]+i*x[rs2], without EEW scaling; positive, negative and zero strides are supported. rs2=x0 permits fewer than one access per active element; a non-x0 register containing zero still requires one access per active element. Strided accesses are unordered, with no guaranteed final value at overlapping addresses.
Require V 1.0, enabled vector state, vill=0 and supported vtype/EEW. v0 cannot supply both EEW=1 mask and data. Only mask-enabled vstart<=i<vl elements access memory; inactive/tail and vstart>=vl (including vl=0) make no access. Misalignment may succeed or fault, and active accesses may trap. Sources stay unchanged; normal completion resets vstart=0.

Pitfalls / Common Confusions

The 16 in the mnemonic is memory element width EEW; the address increment comes from byte-count x[rs2] and is not implicitly scaled again by 2.

The stride may be positive, negative, or zero; rs2=x0 is the official zero-stride encoding, x0 is always 0, and implementations may perform fewer than one memory operation per active element for that form.

Masked-off elements do not perform memory writes and do not raise memory exceptions for that element.

Do not rely on element access order to express side-effecting memory or overlapping-address semantics.

FAQ

What unit does VSSE16.V use for stride?

The stride is the byte count in x[rs2]. It is not an element count and is not implicitly multiplied by EEW again; if encoded as rs2=x0, x0 is always 0.

How is VSSE16.V different from unit-stride VSE16.V?

Unit-stride access advances by consecutive 2-byte elements; VSSE16.V uses byte stride x[rs2], so it can access structure fields, matrix columns, or reverse sequences.

Is rs2=x0 different from x[rs2]=0 for VSSE16.V?

Yes. rs2=x0 permits fewer memory operations than active elements. With rs2!=x0 and x[rs2]=0, one access per active element is required. Both forms are unordered.

Do elements disabled by v0.t access memory?

No. With vm=0, a body element whose v0.t bit is 0 does not perform that element's store memory access.