Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VSE16.V
RISC-V VSE16.V Instruction Details
Instruction ManualV-typeStore active 16-bit elements from vs3 to contiguous memory starting at x[rs1].
Instruction Syntax
vse16.v vs3, (rs1), vm
Operand Breakdown
vs3: source vector register group providing active elements to store.
rs1: integer base-address register; unit-stride forms write consecutive addresses.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector MemoryVector Store
Instruction Behavior
VSE16.V is a RISC-V V 16-bit unit-stride vector store. Active body elements write vs3[i] as a 16-bit memory element to consecutive addresses x[rs1] + i * 2 bytes; with vm=0, v0.t selects elements and masked-off elements do not write memory.
VSE16.V Decode And Execute Animation
Decode the 16-bit unit-stride store, then compute each element address as x[rs1] + i * 2.
Instruction input
vse16.v
Execution context: EEW=16, unit stride=2 bytes, example SEW=16, LMUL=m1. These are not assembly syntax operands.
Encoding fieldsvse16.v / STORE-FP
31..29
nf
000
28
mew
0
27..26
mop
00
25
vm
0
24..20
sumop
00000
19..15
rs1
01010
14..12
width
101
11..7
vd/vs3
01000
6..0
opcode
0100111
Address and data pathaddr[i] = 0x8000 + i * 2
i=0
i=1
i=2
i=3
i=4
i=5
i=6
i=7
i=8
i=9
i=10
i=11
i=12
i=13
i=14
i=15
addr
0x8000
0x8002
0x8004
0x8006
0x8008
0x800a
0x800c
0x800e
0x8010
0x8012
0x8014
0x8016
0x8018
0x801a
0x801c
0x801e
v8
0x0011
0x0022
0x0033
0x0044
0x0055
0x0066
0x0077
0x0088
0x0099
0x00aa
0x00bb
0x00cc
0x00dd
0x00ee
0x00ff
0x0110
active
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
memory write
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Step 1 / 22
Show vector memory instruction encoding
The animation starts from the 32-bit vector memory encoding and shows the official bit fields: nf, mew, mop, vm, rs2/vs2 or lumop/sumop, width, register fields, and opcode.
Quick Understanding & Search Notes
VSE16.V is an RVV 16-bit unit-stride vector store: each active element uses address x[rs1] + i * 2 bytes to write to memory, and element data is taken from source vector register group vs3. vl and the v0.t mask decide which body elements actually access memory.
The mnemonic fixes memory element width EEW=16; unit-stride addresses advance by EEW/8 bytes, not by an arbitrary index scale or by the textual SEW alone.
The unit-stride form starts at x[rs1] and accesses consecutive element addresses; strided and indexed/gather/scatter access use other families such as vlse/vsse, vluxei/vloxei, and vsuxei/vsoxei.
With vm=0, v0.t selects participating body elements; with vm=1, all body elements participate. Masked-off elements do not perform memory accesses.
Stores produce memory writes only for active elements; masked-off elements do not write memory and should not be visualized as writing zero.
Vector Execution Context
When reading VSE16.V, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Contiguous Array Write
Understand this scenario with real code like «vse16.v v8, (a0), v0.t».
Vectorized Memory Access
Understand this scenario with real code like «vse16.v v8, (a0), v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is V-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
The 16 in the mnemonic is memory element width EEW; the address step is 2 bytes.
Unit-stride access uses consecutive addresses; do not treat it as indexed gather/scatter.
Masked-off elements do not perform memory writes, and they do not write zero to memory.
FAQ
Does VSE16.V automatically set vl?
No. vl/vtype are set by an earlier vsetvli, vsetivli, or vsetvl; vector loads and stores execute under the current configuration.
How are unit-stride store addresses calculated?
Active element i uses x[rs1] + i * 2 bytes. This is contiguous memory access, not arbitrary gather/scatter.
Do elements disabled by v0.t access memory?
No. With vm=0, a body element whose v0.t bit is 0 does not perform that element's store memory access.