What unit do VSE64.V offsets or strides use?
Unit-stride stores advance through consecutive element addresses by data EEW.
VSE64.V
RISC-V VSE64.V Instruction Details
Instruction ManualS-typeunit-stride vector store.
Instruction Syntax
vse64.v vs3, (rs1), vm
Operand Breakdown
Source rs2: register holding data to write to memory.
Base rs1: register holding the base address.
Immediate offset: 12-bit signed value added to rs1 for the final address.
VVector MemoryStore
Related Search Terms
Instruction Behavior
VSE64.V stores active 64-bit elements from vs3 contiguously starting at x[rs1]. With vm=0, v0 selects stored elements; vm=1 is unmasked.
Quick Understanding & Search Notes
VSE64.V is an RVV unit-stride store; memory writes occur only for active elements not masked off.
The 64 in the mnemonic is the stored data EEW.
The unit-stride form accesses consecutive element addresses.
vm=0 uses v0 as the execution mask; masked-off elements do not perform memory writes.
Common Usage Scenarios
Contiguous Array Write
Understand this scenario with real code like «vse64.v v8, (a0), v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is S-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
The 64 in the mnemonic is the data EEW; effective EMUL is derived from EEW/SEW and LMUL.
Unit-stride stores contiguous elements starting at the base address.
Masked-off elements do not access memory and do not raise exceptions.