Does ei16 select the stored data width?
No. Indexes are 16-bit unsigned byte offsets; the stored data width comes from current SEW.
VSUXEI16.V
RISC-V VSUXEI16.V Instruction Details
Instruction ManualV-typeUse x[rs1] plus 16-bit unsigned byte offsets from vs2 for unordered indexed stores from active vs3 elements.
Instruction Syntax
vsuxei16.v vs3, (rs1), vs2, vm
Operand Breakdown
vs3 supplies data (EEW=SEW, EMUL=LMUL); vs2 supplies 16-bit unsigned byte offsets with index EMUL=(16/SEW)*LMUL in 1/8..8. Group starts must align; a register cannot supply different source EEWs.
32-bit STORE-FP: opcode=0100111, nf=000, mew=0, mop=01, width=101; vm at bit25, vs2 at bits24:20, rs1 at bits19:15, vs3 at bits11:7.
Active addresses are x[rs1]+zero_extend(vs2[i]), without data-width scaling; x0 supplies base zero. Unordered accesses guarantee neither element order nor final values at duplicate/overlapping addresses. Sources stay unchanged; misalignment may succeed or fault, and other active accesses may trap.
Require RV32/RV64 V 1.0, enabled vector state, vill=0 and supported vtype/SEW/index EEW. v0.t means vm=0; omission means vm=1. Only mask-enabled vstart<=i<vl elements access memory; inactive/tail make no access. vstart>=vl (including vl=0) makes no access; v0 cannot supply both EEW=1 mask and data. Success resets vstart=0.
VVector MemoryIndexed Vector Store
Instruction Behavior
VSUXEI16.V is a RISC-V V-extension unordered indexed vector store instruction. Each active element forms its address as x[rs1] + zero_extend(vs2[i]) and stores the current-SEW data from vs3[i]; ei16 specifies only the index EEW. The unordered form does not guarantee observation in element-number order. With vm=0, elements disabled by v0.t do not write memory.
VSUXEI16.V Decode And Execute Animation
Decode the 16-bit indexed store, then compute each element address as x[rs1] + zero_extend(vs2[i]).
Instruction input
vsuxei16.v
Execution Context
Execution context: index EEW=16, data SEW=32, index EEW=16 is narrower than XLEN=64, so it is zero-extended before addition, unordered indexed accesses do not guarantee element order, LMUL=m1, vstart=0 (a nonzero value starts at that element). These are not assembly syntax operands.
Teaching context: V 1.0, enabled vector state, valid supported vtype/SEW/index EEW; fix VLEN=4096, LMUL=m1, vstart=0, VLMAX=4096/32, index EMUL=0.5. Index groups align and stay within v31; a register cannot supply different source EEWs, and v0.t excludes v0 data sources. Equal-EEW vs3/vs2 sharing a register require equal elements. x0 gives base zero. Assume all active accesses succeed; misaligned accesses require environment support. The address display range 0..0xffffffff is a teaching limit, not an ISA limit. Rows show per-element store events, not a final byte-memory image; later overlapping stores may overwrite earlier data. Unordered stores guarantee neither element access order nor the final value at overlapping addresses; stages are not actual access order. Stages are not processor cycles. Inactive/tail elements make no access; VL=0 makes no access. Sources remain unchanged; success resets vstart=0.
Encoding fieldsvsuxei16.v / STORE-FP
31..29
nf
000
28
mew
0
27..26
mop
01
25
vm
0
24..20
vs2
00100
19..15
rs1
01010
14..12
width
101
11..7
vd/vs3
01100
6..0
opcode
0100111
Address and data pathaddr[i] = 0x8000 + zero_extend(vs2[i])
i=0
i=1
i=2
i=3
i=4
i=5
i=6
i=7
i=8
i=9
i=10
i=11
i=12
i=13
i=14
i=15
vs2 byte offset
0x0001
0x0004
0x0007
0x000a
0x000d
0x0010
0x0013
0x0016
0x0019
0x001c
0x001f
0x0022
0x0025
0x0028
0x002b
0x002e
addr
0x8001
0x8004
0x8007
0x800a
0x800d
0x8010
0x8013
0x8016
0x8019
0x801c
0x801f
0x8022
0x8025
0x8028
0x802b
0x802e
v12
0x00000101
0x00000202
0x00000303
0x00000404
0x00000505
0x00000606
0x00000707
0x00000808
0x00000909
0x00000a0a
0x00000b0b
0x00000c0c
0x00000d0d
0x00000e0e
0x00000f0f
0x00001010
active
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
memory write
...
...
-
...
...
...
...
-
...
...
...
...
-
...
...
...
Step 1 / 22
Show vector memory instruction encoding
The animation starts from the 32-bit vector memory encoding and shows the official bit fields: nf, mew, mop, vm, rs2/vs2 or lumop/sumop, width, register fields, and opcode.
Quick Understanding & Search Notes
VSUXEI16.V is an RVV unordered indexed store; memory writes occur only for active elements not masked off.
32-bit STORE-FP: opcode=0100111, nf=000, mew=0, mop=01, width=101. vm=0 uses v0.t; omission means vm=1. vs3 supplies store data.
ei16 selects index EEW=16 only. Data EEW=SEW, EMUL=LMUL; index EMUL=(16/SEW)*LMUL must be 1/8..8 with aligned groups. A register cannot supply different source EEWs; v0 cannot supply both mask and data.
Active addresses are x[rs1]+zero_extend(vs2[i]), using unscaled unsigned byte offsets. Unordered accesses do not guarantee element order or final values at duplicate/overlapping addresses.
Require RV32/RV64 V 1.0, enabled vector state, vill=0 and supported vtype/index EEW. Only mask-enabled vstart<=i<vl accesses memory; inactive/tail and vstart>=vl (including vl=0) make no access.
Active accesses may trap. Misalignment may succeed or raise an address-misaligned exception. Sources stay unchanged; success resets vstart=0, and x0 supplies base zero.
Vector Execution Context
vs3 supplies data (EEW=SEW, EMUL=LMUL); vs2 supplies 16-bit unsigned byte offsets with index EMUL=(16/SEW)*LMUL in 1/8..8. Group starts must align; a register cannot supply different source EEWs.
32-bit STORE-FP: opcode=0100111, nf=000, mew=0, mop=01, width=101; vm at bit25, vs2 at bits24:20, rs1 at bits19:15, vs3 at bits11:7.
Active addresses are x[rs1]+zero_extend(vs2[i]), without data-width scaling; x0 supplies base zero. Unordered accesses guarantee neither element order nor final values at duplicate/overlapping addresses. Sources stay unchanged; misalignment may succeed or fault, and other active accesses may trap.
Require RV32/RV64 V 1.0, enabled vector state, vill=0 and supported vtype/SEW/index EEW. v0.t means vm=0; omission means vm=1. Only mask-enabled vstart<=i<vl elements access memory; inactive/tail make no access. vstart>=vl (including vl=0) makes no access; v0 cannot supply both EEW=1 mask and data. Success resets vstart=0.
Common Usage Scenarios
Sparse data writes
Assume enabled V/VS, valid m1,tu,mu, VLEN=4096, vl=4, vstart=0, v0.mask[0..3]=1101; SEW=32, x10=0x8000, v8=[10,20,30,40], vs2=v4 (EEW=16)=[12,0,8,4]. lane0: [0x800c]=10; lane1: [0x8000]=20; lane3: [0x8004]=40. Assume writable addresses and successful accesses. Lane2 makes no access; events do not represent actual access order. Sources stay unchanged. Success resets vstart=0.
Scatter access without ordering needs
Assume enabled V/VS, valid m1,tu,mu, VLEN=4096, vl=4, vstart=0, v0.mask[0..3]=1101; SEW=32, x10=0x8000, v8=[10,20,30,40], vs2=v4 (EEW=16)=[12,0,8,4]. lane0: [0x800c]=10; lane1: [0x8000]=20; lane3: [0x8004]=40. Assume writable addresses and successful accesses. Lane2 makes no access; events do not represent actual access order. Sources stay unchanged. Success resets vstart=0.
Indirect array stores
Assume enabled V/VS, valid m1,tu,mu, VLEN=4096, vl=4, vstart=0, v0.mask[0..3]=1101; SEW=32, x10=0x8000, v8=[10,20,30,40], vs2=v4 (EEW=16)=[12,0,8,4]. lane0: [0x800c]=10; lane1: [0x8000]=20; lane3: [0x8004]=40. Assume writable addresses and successful accesses. Lane2 makes no access; events do not represent actual access order. Sources stay unchanged. Success resets vstart=0.
Pre-Use Checklist
Syntax Check
- vs3 supplies data (EEW=SEW, EMUL=LMUL); vs2 supplies 16-bit unsigned byte offsets with index EMUL=(16/SEW)*LMUL in 1/8..8. Group starts must align; a register cannot supply different source EEWs.
- 32-bit STORE-FP: opcode=0100111, nf=000, mew=0, mop=01, width=101; vm at bit25, vs2 at bits24:20, rs1 at bits19:15, vs3 at bits11:7.
Semantic Check
- Active addresses are x[rs1]+zero_extend(vs2[i]), without data-width scaling; x0 supplies base zero. Unordered accesses guarantee neither element order nor final values at duplicate/overlapping addresses. Sources stay unchanged; misalignment may succeed or fault, and other active accesses may trap.
- Require RV32/RV64 V 1.0, enabled vector state, vill=0 and supported vtype/SEW/index EEW. v0.t means vm=0; omission means vm=1. Only mask-enabled vstart<=i<vl elements access memory; inactive/tail make no access. vstart>=vl (including vl=0) makes no access; v0 cannot supply both EEW=1 mask and data. Success resets vstart=0.
Pitfalls / Common Confusions
ei16 is the index EEW, not the SEW of the stored data; data element width still comes from current vtype.
vs2[i] is an unsigned byte offset; the address is x[rs1] + zero_extend(vs2[i]), not x[rs1] + i * EEW and not an element number.
Unordered indexed stores do not guarantee element access order; use the ordered indexed form when an address space requires element order.
With vm=0, elements disabled by v0.t perform no memory write and must not be shown as writing zero.
FAQ
Do duplicate or overlapping addresses have a guaranteed final value?
No. Unordered indexed stores do not guarantee element access order; the highest-numbered element is not guaranteed to write last.