Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VSUXEI32.V
RISC-V VSUXEI32.V Instruction Details
Instruction ManualSTORE-FPUse x[rs1] plus 32-bit unsigned byte offsets from vs2 for unordered indexed stores from active vs3 elements.
Instruction Syntax
vsuxei32.v vs3, (rs1), vs2, vm
Operand Breakdown
vs3 supplies SEW/LMUL data, rs1 the integer base (x0 gives zero), and vs2 unsigned EEW=32 byte offsets without data-width scaling. Index EMUL=(32/SEW)*LMUL must be in 1/8..8, with aligned group starts; a register cannot supply different source EEWs.
32-bit STORE-FP: opcode=0100111, nf=000, mew=0, mop=01, width=110; vm at bit25, vs2 at bits24:20, rs1 at bits19:15, vs3 at bits11:7.
Active addresses are x[rs1]+vs2[i], zero-extending indexes narrower than XLEN. RV32/RV64 V are supported. Unordered accesses guarantee neither element order nor final values at overlapping addresses. Sources stay unchanged; misalignment may succeed or fault, and other active accesses may trap.
Require V 1.0, enabled vector state, vill=0 and supported vtype. Optional v0.t means vm=0; omission means vm=1. Only mask-enabled vstart<=i<vl elements access memory; inactive/tail make no access. v0 cannot supply both EEW=1 mask and data. vstart>=vl (including vl=0) makes no access; success resets vstart=0.
VVector MemoryIndexed Vector Store
Instruction Behavior
VSUXEI32.V is a RISC-V V-extension unordered indexed vector store instruction. Each active element forms its address as x[rs1] + zero_extend(vs2[i]) and stores the current-SEW data from vs3[i]; ei32 specifies only the index EEW. The unordered form does not guarantee observation in element-number order. With vm=0, elements disabled by v0.t do not write memory.
VSUXEI32.V Decode And Execute Animation
Decode the 32-bit indexed store, then compute each element address as x[rs1] + zero_extend(vs2[i]).
Instruction input
vsuxei32.v
Execution Context
Execution context: index EEW=32, data SEW=32, index EEW=32 is narrower than XLEN=64, so it is zero-extended before addition, unordered indexed accesses do not guarantee element order, LMUL=m1, vstart=0 (a nonzero value starts at that element). These are not assembly syntax operands.
Teaching context: V 1.0, enabled vector state, valid supported vtype/SEW/index EEW; fix VLEN=4096, LMUL=m1, vstart=0, VLMAX=4096/32, index EMUL=1. Index groups align and stay within v31; a register cannot supply different source EEWs, and v0.t excludes v0 data sources. Equal-EEW vs3/vs2 sharing a register require equal elements. x0 gives base zero. Assume all active accesses succeed; misaligned accesses require environment support. The address display range 0..0xffffffff is a teaching limit, not an ISA limit. Rows show per-element store events, not a final byte-memory image; later overlapping stores may overwrite earlier data. Unordered stores guarantee neither element access order nor the final value at overlapping addresses; stages are not actual access order. Stages are not processor cycles. Inactive/tail elements make no access; VL=0 makes no access. Sources remain unchanged; success resets vstart=0.
Encoding fieldsvsuxei32.v / STORE-FP
31..29
nf
000
28
mew
0
27..26
mop
01
25
vm
0
24..20
vs2
00100
19..15
rs1
01010
14..12
width
110
11..7
vd/vs3
01100
6..0
opcode
0100111
Address and data pathaddr[i] = 0x8000 + zero_extend(vs2[i])
i=0
i=1
i=2
i=3
i=4
i=5
i=6
i=7
i=8
i=9
i=10
i=11
i=12
i=13
i=14
i=15
vs2 byte offset
0x00000001
0x00000004
0x00000007
0x0000000a
0x0000000d
0x00000010
0x00000013
0x00000016
0x00000019
0x0000001c
0x0000001f
0x00000022
0x00000025
0x00000028
0x0000002b
0x0000002e
addr
0x8001
0x8004
0x8007
0x800a
0x800d
0x8010
0x8013
0x8016
0x8019
0x801c
0x801f
0x8022
0x8025
0x8028
0x802b
0x802e
v12
0x00000101
0x00000202
0x00000303
0x00000404
0x00000505
0x00000606
0x00000707
0x00000808
0x00000909
0x00000a0a
0x00000b0b
0x00000c0c
0x00000d0d
0x00000e0e
0x00000f0f
0x00001010
active
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
memory write
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...
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...
...
...
...
-
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...
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-
...
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Step 1 / 22
Show vector memory instruction encoding
The animation starts from the 32-bit vector memory encoding and shows the official bit fields: nf, mew, mop, vm, rs2/vs2 or lumop/sumop, width, register fields, and opcode.
Quick Understanding & Search Notes
VSUXEI32.V is an RVV unordered indexed store; memory writes occur only for active elements not masked off.
The ei32 in the mnemonic is the index EEW, and index values are unsigned byte offsets.
Unordered indexed stores do not guarantee observable order among element stores.
vm=0 uses v0 as the execution mask; masked-off elements do not perform memory writes.
Vector Execution Context
When reading VSUXEI32.V, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Sparse data writes
Assume enabled V/VS, valid m1,tu,mu, VLEN=4096, XLEN=64, vl=4, vstart=0, v0.mask[0..3]=1101; SEW=32, x10=0x8000, v8=[10,20,30,40], v4 (EEW=32)=[12,0,8,4]. lane0: [0x800c]=10; lane1: [0x8000]=20; lane3: [0x8004]=40. Assume writable addresses and successful active accesses; lane2 and tails make no access, events do not specify access order, and sources stay unchanged. Success resets vstart=0.
Scatter access without ordering needs
Assume enabled V/VS, valid m1,tu,mu, VLEN=4096, XLEN=64, vl=4, vstart=0, v0.mask[0..3]=1101; SEW=32, x10=0x8000, v8=[10,20,30,40], v4 (EEW=32)=[12,0,8,4]. lane0: [0x800c]=10; lane1: [0x8000]=20; lane3: [0x8004]=40. Assume writable addresses and successful active accesses; lane2 and tails make no access, events do not specify access order, and sources stay unchanged. Success resets vstart=0.
Indirect array stores
Assume enabled V/VS, valid m1,tu,mu, VLEN=4096, XLEN=64, vl=4, vstart=0, v0.mask[0..3]=1101; SEW=32, x10=0x8000, v8=[10,20,30,40], v4 (EEW=32)=[12,0,8,4]. lane0: [0x800c]=10; lane1: [0x8000]=20; lane3: [0x8004]=40. Assume writable addresses and successful active accesses; lane2 and tails make no access, events do not specify access order, and sources stay unchanged. Success resets vstart=0.
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is STORE-FP.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
ei32 is the index EEW, not the SEW of the stored data; data element width still comes from current vtype.
vs2[i] is an unsigned byte offset; the address is x[rs1] + zero_extend(vs2[i]), not x[rs1] + i * EEW and not an element number.
Unordered indexed stores do not guarantee element access order; use the ordered indexed form when an address space requires element order.
With vm=0, elements disabled by v0.t perform no memory write and must not be shown as writing zero.
FAQ
What unit do VSUXEI32.V offsets or strides use?
Index values are unsigned byte offsets, not element numbers.