VSUXEI64.V

RISC-V VSUXEI64.V Instruction Details

Instruction ManualSTORE-FP

On RV64 V, add 64-bit byte offsets from vs2 to x[rs1] and store active SEW-wide vs3 elements without element-order guarantees.

Instruction Syntax

vsuxei64.v vs3, (rs1), vs2, vm

Operand Breakdown

vs3 supplies SEW/LMUL data, rs1 the integer base (x0 gives zero), and vs2 unsigned EEW=64 byte offsets without data-width scaling. Index EMUL=(64/SEW)*LMUL must be in 1/8..8, with aligned group starts; a register cannot supply different source EEWs.

32-bit STORE-FP: opcode=0100111, nf=000, mew=0, mop=01, width=111; vm at bit25, vs2 at bits24:20, rs1 at bits19:15, vs3 at bits11:7.

Active addresses are x[rs1]+vs2[i], zero-extending indexes narrower than XLEN. V does not support 64-bit indexes on RV32; the generic low-XLEN rule does not override this limit. Unordered accesses guarantee neither element order nor final values at overlapping addresses. Sources stay unchanged; misalignment may succeed or fault, and other active accesses may trap.

Require V 1.0, enabled vector state, vill=0 and supported vtype. Optional v0.t means vm=0; omission means vm=1. Only mask-enabled vstart<=i<vl elements access memory; inactive/tail make no access. v0 cannot supply both EEW=1 mask and data. vstart>=vl (including vl=0) makes no access; success resets vstart=0.

VVector MemoryIndexed Vector Store

Related Search Terms

VSUXEI64.V instruction RISC-V VSUXEI64.V vsuxei64.v syntax vsuxei64.v encoding RVV indexed store ei64 index unordered indexed store

Instruction Behavior

VSUXEI64.V is an unordered indexed vector store in the RISC-V V extension. On RV64, active elements use x[rs1]+vs2[i] and store current-SEW data; ei64 specifies index EEW=64. V does not support 64-bit indexes on RV32; the generic low-XLEN rule does not override this limit. Element access order is not guaranteed; masked-off elements make no memory access.

VSUXEI64.V Decode And Execute Animation

Decode the 64-bit indexed store, then compute each element address as x[rs1] + vs2[i].

Instruction input

vsuxei64.v

vs3Vector register v0-v31rs1Integer base-address registervs2Index vector register v0-v31vmexecution mask control

Execution Context

VLSEWXLENx[rs1]vs2 index bytes (64)0..0xffffffffffffffff, unsigned byte offsetsvs3 elements0..0xffffffff, comma-separatedv0 mask bits0/1 only, length equals VL

Execution context: index EEW=64, data SEW=32, index EEW and XLEN are both 64, so the full index value is used, unordered indexed accesses do not guarantee element order, LMUL=m1, vstart=0 (a nonzero value starts at that element). These are not assembly syntax operands.

Teaching context: V 1.0, enabled vector state, valid supported vtype/SEW/index EEW; fix VLEN=4096, LMUL=m1, vstart=0, VLMAX=4096/32, index EMUL=2. Index groups align and stay within v31; a register cannot supply different source EEWs, and v0.t excludes v0 data sources. Equal-EEW vs3/vs2 sharing a register require equal elements. x0 gives base zero. Assume all active accesses succeed; misaligned accesses require environment support. The address display range 0..0xffffffff is a teaching limit, not an ISA limit. Rows show per-element store events, not a final byte-memory image; later overlapping stores may overwrite earlier data. Unordered stores guarantee neither element access order nor the final value at overlapping addresses; stages are not actual access order. Stages are not processor cycles. Inactive/tail elements make no access; VL=0 makes no access. Sources remain unchanged; success resets vstart=0.

Encoding fieldsvsuxei64.v / STORE-FP

31..29

000

mew

27..26

mop

24..20

vs2

00100

19..15

rs1

01010

14..12

width

111

11..7

vd/vs3

01100

6..0

opcode

0100111

Address and data pathaddr[i] = 0x8000 + vs2[i]

i=0

i=1

i=2

i=3

i=4

i=5

i=6

i=7

i=8

i=9

i=10

i=11

i=12

i=13

i=14

i=15

vs2 byte offset

0x0000000000000001

0x0000000000000004

0x0000000000000007

0x000000000000000a

0x000000000000000d

0x0000000000000010

0x0000000000000013

0x0000000000000016

0x0000000000000019

0x000000000000001c

0x000000000000001f

0x0000000000000022

0x0000000000000025

0x0000000000000028

0x000000000000002b

0x000000000000002e

addr

0x8001

0x8004

0x8007

0x800a

0x800d

0x8010

0x8013

0x8016

0x8019

0x801c

0x801f

0x8022

0x8025

0x8028

0x802b

0x802e

v12

0x00000101

0x00000202

0x00000303

0x00000404

0x00000505

0x00000606

0x00000707

0x00000808

0x00000909

0x00000a0a

0x00000b0b

0x00000c0c

0x00000d0d

0x00000e0e

0x00000f0f

0x00001010

active

memory write

...

Step 1 / 22

Show vector memory instruction encoding

The animation starts from the 32-bit vector memory encoding and shows the official bit fields: nf, mew, mop, vm, rs2/vs2 or lumop/sumop, width, register fields, and opcode.

Quick Understanding & Search Notes

VSUXEI64.V is an RVV unordered indexed store; memory writes occur only for active elements not masked off.

The ei64 in the mnemonic is the index EEW, and index values are unsigned byte offsets.

RV64 uses the full ei64 index; V does not support 64-bit indexes on RV32. The generic low-XLEN rule does not override this limit.

Unordered indexed stores do not guarantee observable order among element stores.

vm=0 uses v0 as the execution mask; masked-off elements do not perform memory writes.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture

Vector Execution Context

When reading VSUXEI64.V, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Sparse data writes

Assume enabled V/VS, valid m1,tu,mu, VLEN=4096, XLEN=64, vl=4, vstart=0, v0.mask[0..3]=1101; SEW=32, x10=0x8000, v8=[10,20,30,40], v4 (EEW=64)=[12,0,8,4]. lane0: [0x800c]=10; lane1: [0x8000]=20; lane3: [0x8004]=40. Assume writable addresses and successful active accesses; lane2 and tails make no access, events do not specify access order, and sources stay unchanged. Success resets vstart=0.

Scatter access without ordering needs

Indirect array stores

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is STORE-FP.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

ei64 is the index EEW, not the SEW of the stored data; data element width still comes from current vtype.

vs2[i] is an unsigned byte offset, not x[rs1] + i * EEW and not an element number. ei64 uses the full index in RV64; V does not support 64-bit indexes on RV32.

Unordered indexed stores do not guarantee element access order; use the ordered indexed form when an address space requires element order.

With vm=0, elements disabled by v0.t perform no memory write and must not be shown as writing zero.

FAQ

What unit do VSUXEI64.V offsets or strides use?

Index values are unsigned byte offsets, not element numbers.