What unit do VSUXEI8.V offsets or strides use?
Index values are unsigned byte offsets, not element numbers.
VSUXEI8.V
RISC-V VSUXEI8.V Instruction Details
Instruction ManualS-typeunordered indexed vector store.
Instruction Syntax
vsuxei8.v vs3, (rs1), vs2, vm
Operand Breakdown
Source rs2: register holding data to write to memory.
Base rs1: register holding the base address.
Immediate offset: 12-bit signed value added to rs1 for the final address.
VVector Operations
Related Search Terms
Instruction Behavior
VSUXEI8.V stores active elements from vs3 at byte-offset addresses x[rs1] + vs2[i]; no observable order is guaranteed among element stores. The index EEW is 8 bits. With vm=0, v0 selects stored elements; vm=1 is unmasked.
Quick Understanding & Search Notes
VSUXEI8.V is an RVV unordered indexed store; memory writes occur only for active elements not masked off.
The ei8 in the mnemonic is the index EEW, and index values are unsigned byte offsets.
Unordered indexed stores do not guarantee observable order among element stores.
vm=0 uses v0 as the execution mask; masked-off elements do not perform memory writes.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «vsuxei8.v v8, (a0), v4, v0.t».
Data Storing
Understand this scenario with real code like «vsuxei8.v v8, (a0), v4, v0.t».
Vector Operations
Understand this scenario with real code like «vsuxei8.v v8, (a0), v4, v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is S-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
ei8 is the index EEW; data width is still interpreted using current SEW/LMUL.
vs2[i] is an unsigned byte offset, not an element number.
Unordered indexed stores do not guarantee observable element access order.