RVOPcode
Home/Instructions/VSUXEI8-V
VSUXEI8.V

RISC-V VSUXEI8.V Instruction Details

Instruction ManualV-type

Use x[rs1] plus 8-bit unsigned byte offsets from vs2 for unordered indexed stores from active vs3 elements.

Instruction Syntax

vsuxei8.v vs3, (rs1), vs2, vm
Operand Breakdown
vs3: source vector register group providing active elements to store.
rs1: integer base-address register; unit-stride forms write consecutive addresses.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector MemoryIndexed Vector Store
Related Search Terms
VSUXEI8.V instructionRISC-V VSUXEI8.Vvsuxei8.v syntaxvsuxei8.v encodingRVV indexed storeei8 indexunordered indexed store

Instruction Behavior

VSUXEI8.V is an RISC-V V-extension unordered indexed vector store instruction. Each active element forms its address as x[rs1] + zero_extend(vs2[i]) and stores the current-SEW data from vs3[i]; ei8 specifies only the index EEW. The unordered form does not guarantee observation in element-number order. With vm=0, elements disabled by v0.t do not write memory.

VSUXEI8.V Decode And Execute Animation

Decode the 8-bit indexed store, then compute each element address as x[rs1] + zero_extend(vs2[i]).

Instruction input
vsuxei8.v
Execution context: index EEW=8, data SEW=32, address=x[rs1]+zero_extend(vs2[i]), unordered indexed accesses do not guarantee element order, LMUL=m1. These are not assembly syntax operands.
Encoding fieldsvsuxei8.v / STORE-FP
31..29
nf
000
28
mew
0
27..26
mop
01
25
vm
0
24..20
vs2
00100
19..15
rs1
01010
14..12
width
000
11..7
vd/vs3
01100
6..0
opcode
0100111
Address and data pathaddr[i] = 0x8000 + vs2[i]
i=0
i=1
i=2
i=3
i=4
i=5
i=6
i=7
i=8
i=9
i=10
i=11
i=12
i=13
i=14
i=15
vs2 byte offset
0x00
0x0c
0x18
0x18
0x24
0x30
0x30
0x3c
0x48
0x48
0x54
0x60
0x60
0x6c
0x78
0x78
addr
0x8000
0x800c
0x8018
0x8018
0x8024
0x8030
0x8030
0x803c
0x8048
0x8048
0x8054
0x8060
0x8060
0x806c
0x8078
0x8078
v12
0x00000101
0x00000202
0x00000303
0x00000404
0x00000505
0x00000606
0x00000707
0x00000808
0x00000909
0x00000a0a
0x00000b0b
0x00000c0c
0x00000d0d
0x00000e0e
0x00000f0f
0x00001010
active
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
memory write
...
...
-
...
...
...
...
-
...
...
...
...
-
...
...
...
Step 1 / 22

Show vector memory instruction encoding

The animation starts from the 32-bit vector memory encoding and shows the official bit fields: nf, mew, mop, vm, rs2/vs2 or lumop/sumop, width, register fields, and opcode.

Quick Understanding & Search Notes

VSUXEI8.V is an RVV unordered indexed store; memory writes occur only for active elements not masked off.

The ei8 in the mnemonic is the index EEW, and index values are unsigned byte offsets.
Unordered indexed stores do not guarantee observable order among element stores.
vm=0 uses v0 as the execution mask; masked-off elements do not perform memory writes.
RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations

Vector Execution Context

When reading VSUXEI8.V, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Sparse data writes

Understand this scenario with real code like «vsuxei8.v v8, (a0), v4, v0.t».

Scatter access without ordering needs

Understand this scenario with real code like «vsuxei8.v v8, (a0), v4, v0.t».

Indirect array stores

Understand this scenario with real code like «vsuxei8.v v8, (a0), v4, v0.t».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is V-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

ei8 is the index EEW, not the SEW of the stored data; data element width still comes from current vtype.
vs2[i] is an unsigned byte offset; the address is x[rs1] + zero_extend(vs2[i]), not x[rs1] + i * EEW and not an element number.
Unordered indexed stores do not guarantee element access order; use the ordered indexed form when an address space requires element order.
With vm=0, elements disabled by v0.t perform no memory write and must not be shown as writing zero.

FAQ

What unit do VSUXEI8.V offsets or strides use?

Index values are unsigned byte offsets, not element numbers.