What unit do VSSE8.V offsets or strides use?
The stride is a byte count from x[rs2].
VSSE8.V
RISC-V VSSE8.V Instruction Details
Instruction ManualS-typestrided vector store.
Instruction Syntax
vsse8.v vs3, (rs1), rs2, vm
Operand Breakdown
Source rs2: register holding data to write to memory.
Base rs1: register holding the base address.
Immediate offset: 12-bit signed value added to rs1 for the final address.
VVector Operations
Related Search Terms
Instruction Behavior
VSSE8.V stores active 8-bit elements from vs3 at x[rs1] + i*x[rs2]. With vm=0, v0 selects stored elements; vm=1 is unmasked.
Quick Understanding & Search Notes
VSSE8.V is an RVV strided store; memory writes occur only for active elements not masked off.
The 8 in the mnemonic is the stored data EEW.
The stride comes from x[rs2] and is measured in bytes.
vm=0 uses v0 as the execution mask; masked-off elements do not perform memory writes.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «vsse8.v v8, (a0), t0, v0.t».
Data Storing
Understand this scenario with real code like «vsse8.v v8, (a0), t0, v0.t».
Vector Operations
Understand this scenario with real code like «vsse8.v v8, (a0), t0, v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is S-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
The 8 in the mnemonic is the data EEW; effective EMUL is derived from EEW/SEW and LMUL.
The stride comes from scalar x[rs2] and is measured in bytes.
Masked-off elements do not access memory and do not raise exceptions.