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VLE8.V

RISC-V VLE8.V Instruction Details

Instruction ManualR-type

Load 8-bit elements into vd from x[rs1] with unit stride.

Instruction Syntax

vle8.v vd, (rs1), vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
VVector LoadMemory Access
Related Search Terms
VLE8.V instructionRISC-V VLE8.Vvle8.v syntaxvle8.v RVV8-bit loadunit-stride load

Instruction Behavior

VLE8.V is a RISC-V V 8-bit unit-stride vector load instruction. Active elements are loaded from consecutive memory addresses using natural unit stride. It operates on active elements within vl, with masking and tail behavior following RVV rules.

Quick Understanding & Search Notes

Unit-stride loads are for contiguous memory, and the instruction name fixes EEW.

EEW=8; destination elements are interpreted under the current SEW/LMUL configuration and instruction EEW rules.
The unit-stride form accesses consecutive element addresses and suits arrays or contiguous fields.
vm=0 uses v0 as the execution mask and vm=1 is unmasked; inactive and tail elements follow the current vma/vta policy.
RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations

Common Usage Scenarios

Memory Load

Understand this scenario with real code like «vsetvli t0, a0, e8, m1, ta, ma vle8.v v1, (a0)».

Array Traversal

Understand this scenario with real code like «vsetvli t0, a0, e8, m1, ta, ma vle8.v v1, (a0)».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

The instruction EEW=8 fixes the memory element width; the current vtype must make the derived EEW/SEW EMUL legal.
vm=0 uses v0 to mask elements and vm=1 is unmasked; masked-off elements do not perform memory accesses.

FAQ

What unit is used for VLE8.V address offsets?

Unit-stride loads advance by the instruction EEW for consecutive elements.

How does VLE8.V handle masking?

With vm=0, v0 selects active elements; with vm=1, all body elements participate. Inactive and tail elements follow the current policies.