Can VMV.V.X take v0.t?
No. VMV.V is an unmasked move form; use VMERGE when conditional selection under v0 is required.
VMV.V.X
RISC-V VMV.V.X Instruction Details
Instruction ManualOPIVXBroadcasts integer scalar rs1 to vd body elements as an unmasked vector move.
Instruction Syntax
vmv.v.x vd, rs1
Operand Breakdown
vd is a group at current LMUL; rs1 is an integer scalar source.
32-bit OP-V: opcode=1010111, funct6=010111, funct3=100, vm=1; vs2=00000 is fixed; no v0.t operand.
XLEN>SEW takes low scalar bits; XLEN<SEW sign-extends; x0 supplies zero. Body is vstart≤i<vl; tails follow vta and vma does not affect this unmasked form. vl=0 updates no destination elements.
Require V 1.0, valid supported vtype and non-Off mstatus.VS; with H and virtualization V=1, vsstatus.VS must also be non-Off. Successful completion resets vstart to 0.
VVector Data MovementScalar-Vector Transfer
Instruction Behavior
VMV.V.X is an unmasked vector integer move form in the RISC-V V extension. It broadcasts integer scalar rs1 to vd body elements; the encoding fixes vm=1 and vs2=v0, and the syntax has no v0.t execution mask.
VMV.V.X Decode And Execute Animation
Starts from OP-V encoding fields, then shows how the unmasked VMV.V move form writes the current source value into vd body elements.
Instruction input
vmv.v.x
Execution Context
The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. It fixes VLEN=4096, VLMAX=4096/16=256, and assumes support for the selected SEW; equal vector sources require equal elements. VMV.V fixes vm=1 and vs2=0; vector sources copy, while scalars broadcast by the XLEN/SEW rule. Tails follow vtype.vta; vma does not affect body.
OP-V encodingvmv.v.x
funct6
010111
vm
1
vs2
00000
rs1
01011
funct3
100
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
copy
copy
copy
copy
copy
copy
copy
copy
x11
0x0055
0x0055
0x0055
0x0055
0x0055
0x0055
0x0055
0x0055
active
1
1
1
1
1
1
1
1
v4
...
...
...
...
...
...
...
...
Current step
Show OP-V 32-bit encoding fields
vmv.v.x uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer broadcast, fixed unmasked move, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VMV.V.X is an unmasked VMV.V scalar broadcast form that broadcasts the SEW-width value formed from x[rs1] by the .vx rule to vd body elements. It performs no arithmetic and no memory access.
Require V 1.0, valid supported vtype and non-Off mstatus.VS; with H and virtualization V=1, vsstatus.VS must also be non-Off.
32-bit OP-V: funct6=010111, funct3=100, vm=1, vs2=00000; syntax has only vd and rs1, with no v0.t.
Every body element vstart≤i<vl copies the source; prestart is unchanged. Tails follow vta: retain old values or permit all ones; vma does not select body elements.
rs1 is an integer source: XLEN>SEW takes low SEW bits; XLEN<SEW sign-extends to SEW; x0 supplies zero.
vstart≥vl (including vl=0) updates no destination elements; successful completion resets vstart to 0.
Vector Execution Context
vd is a group at current LMUL; rs1 is an integer scalar source.
32-bit OP-V: opcode=1010111, funct6=010111, funct3=100, vm=1; vs2=00000 is fixed; no v0.t operand.
XLEN>SEW takes low scalar bits; XLEN<SEW sign-extends; x0 supplies zero. Body is vstart≤i<vl; tails follow vta and vma does not affect this unmasked form. vl=0 updates no destination elements.
Require V 1.0, valid supported vtype and non-Off mstatus.VS; with H and virtualization V=1, vsstatus.VS must also be non-Off. Successful completion resets vstart to 0.
Common Usage Scenarios
Vector initialization
Assume enabled V/VS, valid m1, VLEN≥128, initialized sources and vstart=0; XLEN=64, e8, x5=0x180, vl=4 → v1[0..3]=[0x80,0x80,0x80,0x80]. Tails follow vta without assumed zeroing.
Integer scalar broadcast
Assume enabled V/VS, valid m1, VLEN≥128, initialized sources and vstart=0; XLEN=64, e8, x5=0x180, vl=4 → v1[0..3]=[0x80,0x80,0x80,0x80]. Tails follow vta without assumed zeroing.
Pre-Use Checklist
Syntax Check
- vd is a group at current LMUL; rs1 is an integer scalar source.
- 32-bit OP-V: opcode=1010111, funct6=010111, funct3=100, vm=1; vs2=00000 is fixed; no v0.t operand.
Semantic Check
- XLEN>SEW takes low scalar bits; XLEN<SEW sign-extends; x0 supplies zero. Body is vstart≤i<vl; tails follow vta and vma does not affect this unmasked form. vl=0 updates no destination elements.
- Require V 1.0, valid supported vtype and non-Off mstatus.VS; with H and virtualization V=1, vsstatus.VS must also be non-Off. Successful completion resets vstart to 0.
Pitfalls / Common Confusions
VMV.V is an unmasked move form, and the syntax has no v0.t.
The encoding fixes vs2=v0 and vm=1; do not interpret it as conditional execution under v0.
Tail elements still follow the current tail policy.
FAQ
Does VMV.V.X access memory or perform arithmetic?
No. It only broadcasts bit patterns through registers and current body elements.