Check vl first
Body elements satisfy vstart ≤ i < vl; vstart≥vl leaves the destination unchanged. Set supported vl/vtype and initialize the sources and v0 first.
VADD.VX
RISC-V VADD.VX Instruction Details
Instruction ManualOPIVXVADD.VX adds an integer scalar to active elements, wrapping at SEW bits.
Instruction Syntax
vadd.vx vd, vs2, rs1[, v0.t]
Operand Breakdown
vd and vs2 are SEW-wide vector groups; same-EEW destination/source overlap is allowed and equal sources read identical initial values.
rs1 is an x-register: take low SEW bits for XLEN>SEW, sign-extend for XLEN<SEW; x0 supplies zero.
Require V and supported vtype. Active body: vstart≤i<vl and (vm=1 or v0.mask[i]=1); vstart≥vl leaves the destination unchanged.
Omitting the mask means vm=1; v0.t means vm=0. Inactive/tail follow vma/vta; masked vd cannot cover v0, and v0 cannot be read at both EEW=1 and SEW.
VVector OperationsInteger Arithmetic
Instruction Behavior
Require V and supported vtype. Active elements compute vs2[i] + scalar, retaining low SEW bits. Use low SEW bits of x[rs1] when XLEN>SEW, sign-extend when XLEN<SEW; x0 supplies zero. Body: vstart≤i<vl. vm=0 selects with v0.t; omitting the mask means vm=1. Inactive/tail elements follow vma/vta.
VADD.VX Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VADD single-width integer add reads active elements, wraps at SEW, and writes vd.
Instruction input
vadd.vx
Require valid vtype, enabled VS, and supported SEW; VL=0 updates nothing, including tails. Steps are teaching stages, not processor cycles.
Execution Context
The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. It fixes VLEN=4096, VLMAX=4096/16=256, and assumes support for the selected SEW; equal vector sources require equal elements. In ordinary masked forms, inactive and tail elements follow vtype.vma/vta and the result row does not invent a definite value; VADC/VMADC/VSBC/VMSBC execute every body element, with v0 bits used only as carry/borrow-in.
OP-V encodingvadd.vx
funct6
000000
vm
0
vs2
01000
rs1
01011
funct3
100
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x00fa
0x010b
0x011c
0x012d
0x013e
0x014f
0x0160
0x0171
+
+
+
+
+
+
+
+
x11
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vadd.vx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer addition, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
vs2[i] + scalar; Use low SEW bits of x[rs1] when XLEN>SEW, sign-extend when XLEN<SEW; x0 supplies zero.
32-bit OP-V: opcode=1010111, funct6=000000, funct3=100 (OPIVX).
Active body: vstart≤i<vl and (unmasked or v0.mask[i]=1); vstart≥vl leaves the destination unchanged.
Same-EEW destination/source overlap is allowed; equal sources read identical initial values.
Vector Execution Context
When reading VADD.VX, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vx: one vector source and one integer scalar source participate.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
With vm=0, v0.t selects active body elements; omitting the mask operand means vm=1, unmasked. Inactive and tail elements follow current vma/vta.
Common Usage Scenarios
Add one integer scalar to active elements
Assume V with e8,m1, x10=4 giving vl=4, vstart=0, source lanes initialized to vs2=255, x11=1, and v0 bits 1010 in lane order 0..3. vsetvli x5, x10, e8, m1, ta, ma vadd.vx v4, v8, x11, v0.t gives [0,policy,0,policy]; policy follows vma and tails follow vta.
Pre-Use Checklist
Syntax Check
- vd and vs2 are SEW-wide vector groups; same-EEW destination/source overlap is allowed and equal sources read identical initial values.
- rs1 is an x-register: take low SEW bits for XLEN>SEW, sign-extend for XLEN<SEW; x0 supplies zero.
Semantic Check
- Require V and supported vtype. Active body: vstart≤i<vl and (vm=1 or v0.mask[i]=1); vstart≥vl leaves the destination unchanged.
- Omitting the mask means vm=1; v0.t means vm=0. Inactive/tail follow vma/vta; masked vd cannot cover v0, and v0 cannot be read at both EEW=1 and SEW.
Pitfalls / Common Confusions
Use low SEW bits of x[rs1] when XLEN>SEW, sign-extend when XLEN<SEW; x0 supplies zero.
The result does not saturate.
Masked vd cannot overlap v0; v0 cannot supply both the EEW=1 mask and SEW data.
FAQ
How does VADD.VX handle inactive elements?
Follow vma: undisturbed or agnostic, not fixed zero. Tails follow vta.
Does VADD.VX saturate?
No; retain low SEW bits without setting vxsat.