Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VADD.VX
RISC-V VADD.VX Instruction Details
Instruction ManualR-typeAdd each integer element to x[rs1]: vd[i] = vs2[i] + x[rs1].
Instruction Syntax
vadd.vx vd, vs2, rs1, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector OperationsInteger Arithmetic
Instruction Behavior
VADD.VX performs RVV single-width integer addition. Each active element computes vd[i] = vs2[i] + x[rs1], using the same integer scalar source for every active element; the low SEW bits are written back and integer overflow wraps at SEW width. With vm=0, body elements whose mask bit is 0 do not execute this add, and their destination elements follow the current mask policy.
VADD.VX Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VADD single-width integer add reads active elements, wraps at SEW, and writes vd.
Instruction input
vadd.vx
OP-V encodingvadd.vx
funct6
000000
vm
0
vs2
01000
rs1
01011
funct3
100
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x00fa
0x010b
0x011c
0x012d
0x013e
0x014f
0x0160
0x0171
+
+
+
+
+
+
+
+
x11
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vadd.vx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer addition, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VADD.VX adds the same integer scalar x[rs1] to each active element of vs2. It is used when vector data needs the same integer register value added to every active element, with the result still keeping the low SEW bits.
VADD uses OP-V vector-arithmetic encoding with funct6=000000; the .vx form is selected by funct3=100.
vs2 is the vector source and rs1 is the integer scalar source; the same x[rs1] value is used for every active element.
Only body elements within the current vl are processed; vm=0 uses the v0 mask, vm=1 is unmasked, and masked-off destination elements follow the current mask policy.
Integer overflow keeps the low SEW bits and sets no integer or floating-point exception flag; use VSADD/VSADDU for saturating semantics.
Vector Execution Context
When reading VADD.VX, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vx: one vector source and one integer scalar source participate.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Vectorized Loops
Understand this scenario with real code like «vadd.vx v1, v2, t0 # add scalar t0 to each active element».
Array Ops
Understand this scenario with real code like «vadd.vx v1, v2, t0 # add scalar t0 to each active element».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
The second source of VADD.VX is integer register x[rs1], not vector register vs1.
The scalar participates at SEW width in single-width integer addition; the result keeps the low SEW bits and does not saturate.
With vm=0, only body elements whose v0 mask bit is 1 execute this add; all active elements share the same scalar source value.
FAQ
How do I choose VADD.VV, VADD.VX, and VADD.VI?
Use .vv when both operands are vector registers, .vx when one operand is an integer scalar register, and .vi for a small 5-bit signed constant.
Does VADD saturate or set an overflow flag?
No. VADD is ordinary two's-complement addition and keeps the low SEW bits. Saturating add is a separate RVV instruction category.