Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VSUB.VX
RISC-V VSUB.VX Instruction Details
Instruction ManualOPIVXElement-wise vector integer subtraction.
Instruction Syntax
vsub.vx vd, vs2, rs1, vm
Operand Breakdown
vs3: source vector register group providing active elements to store.
rs1: integer base-address register; unit-stride forms write consecutive addresses.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector Operations
Instruction Behavior
VSUB.VX computes vs2[i] - x[rs1] for active elements and writes the low SEW bits to vd.
VSUB.VX Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VSUB subtracts the second source from vs2, wraps at SEW, and writes vd.
Instruction input
vsub.vx
OP-V encodingvsub.vx
funct6
000010
vm
0
vs2
01000
rs1
01011
funct3
100
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x00fa
0x010b
0x011c
0x012d
0x013e
0x014f
0x0160
0x0171
-
-
-
-
-
-
-
-
x11
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vsub.vx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer subtraction, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VSUB.VX computes vs2[i] - x[rs1] for each active element. The scalar is on the right side; use VRSUB.VX for x[rs1] - vs2[i].
This page follows the official RISC-V V extension: vector instructions operate on body elements within the current vl. Unmasked forms operate on all body elements; forms with vm use v0 as the execution mask when vm=0. SEW, LMUL, tail policy, and mask policy come from the current vtype.
VSUB.VX is single-width integer vector-scalar subtraction; the vector operand has EEW=SEW and the scalar comes from integer register rs1.
The `.vx` subtraction direction is vs2 - rs1, not rs1 - vs2.
In OP-V encoding, opcode=1010111 and VSUB uses funct6=000010; the `.vx` form is selected by funct3=100.
The result wraps to the low SEW bits and provides no borrow flag or overflow trap.
Vector Execution Context
When reading VSUB.VX, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vx: one vector source and one integer scalar source participate.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «vsub.vx v1, v2, t0 # v1[i] = v2[i] - t0».
Data Storing
Understand this scenario with real code like «vsub.vx v1, v2, t0 # v1[i] = v2[i] - t0».
Vector Operations
Understand this scenario with real code like «vsub.vx v1, v2, t0 # v1[i] = v2[i] - t0».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is OPIVX.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
The result wraps at SEW width and does not raise integer overflow exceptions.
Operand order is vs2 - vs1/rs1, not the reverse.
Use vrsub when scalar-minus-vector order is required.
FAQ
Is VSUB.VX scalar minus vector?
No. VSUB.VX is vs2[i] - x[rs1]. Use VRSUB.VX for scalar minus vector.
Where does the VSUB.VX scalar come from?
The VX scalar comes from integer register rs1 and is used for each active element.