How is VSUB.VV different from VRSUB?
VSUB.VV subtracts in the vs2[i] - vs1[i] direction. VRSUB is reverse subtraction: scalar or immediate minus vs2[i].
VSUB.VV
RISC-V VSUB.VV Instruction Details
Instruction ManualOPIVVVSUB.VV subtracts vs1 from active vs2 elements, keeping low SEW bits.
Instruction Syntax
vsub.vv vd, vs2, vs1, vm
Operand Breakdown
vd/vs2/vs1 are aligned EEW=SEW, EMUL=LMUL groups. Equal-width source/destination overlap is legal; equal sources read equal values. vs1[i] is the subtrahend.
32-bit OP-V: opcode=1010111, funct6=000010, funct3=000; vm at bit25, vs2 at bits24:20, vs1 at bits19:15, vd at bits11:7.
Active vd[i]=(vs2[i] - vs1[i]) mod 2^SEW, without a borrow flag, integer overflow trap, saturation or vxsat change. VRSUB reverses the subtraction direction.
Require RV32/RV64 V 1.0, enabled vector state, vill=0 and supported vtype/SEW. v0.t means vm=0; omission means vm=1. Only mask-enabled vstart<=i<vl elements compute; prestart stays unchanged, inactive/tail follow vma/vta, retaining or all ones; masked vd excludes v0. vstart>=vl (including vl=0) leaves vd unchanged; v0 cannot supply both EEW=1 mask and data. Success resets vstart=0.
VVector Operations
Instruction Behavior
VSUB.VV computes vs2[i] - vs1[i] for active elements, wrapping at SEW width.
VSUB.VV Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VSUB subtracts the second source from vs2, wraps at SEW, and writes vd.
Instruction input
vsub.vv
Require V 1.0, enabled vector state and valid supported vtype/SEW. Fix LMUL=m1, vstart=0, VLEN=4096 and VLMAX=4096/16=256. An ordinary masked vd cannot be v0; equal-width source/destination overlap is legal. XLEN>SEW takes low scalar bits; XLEN<SEW sign-extends; x0 supplies zero. When v0 supplies the EEW=1 mask it cannot also supply SEW data. VL=0 updates no destination elements. Only body is shown without definite inactive/tail values. Steps are teaching stages, not processor cycles.
Execution Context
OP-V encodingvsub.vv
funct6
000010
vm
0
vs2
01000
vs1
01100
funct3
000
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x00fa
0x010b
0x011c
0x012d
0x013e
0x014f
0x0160
0x0171
-
-
-
-
-
-
-
-
v12
0x000d
0x0016
0x001f
0x0028
0x0031
0x003a
0x0043
0x004c
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vsub.vv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows OP-V field decode, active-element reads, SEW-width integer subtraction, mask control, and vd writeback. These are teaching stages; they do not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VSUB.VV computes vs2[i] - vs1[i] for active elements, wrapping at SEW width.
32-bit OP-V: opcode=1010111, funct6=000010, funct3=000; vs2 is the minuend. Keep low SEW bits without a borrow flag, integer overflow trap or vxsat change.
Require RV32/RV64 V 1.0, enabled vector state, vill=0 and supported vtype/SEW. Active elements have vstart<=i<vl and, with vm=0, v0.mask[i]=1. Omitting v0.t means vm=1.
Prestart stays unchanged; inactive/tail follow vma/vta, retaining old values or becoming all ones. vstart>=vl (including vl=0) updates no destination elements; success resets vstart=0.
Vector EEW=SEW, EMUL=LMUL; group starts must align. Equal-width source/destination overlap is allowed; equal sources read equal values. Masked vd excludes v0, which cannot supply both mask and SEW data.
Vector Execution Context
vd/vs2/vs1 are aligned EEW=SEW, EMUL=LMUL groups. Equal-width source/destination overlap is legal; equal sources read equal values. vs1[i] is the subtrahend.
32-bit OP-V: opcode=1010111, funct6=000010, funct3=000; vm at bit25, vs2 at bits24:20, vs1 at bits19:15, vd at bits11:7.
Active vd[i]=(vs2[i] - vs1[i]) mod 2^SEW, without a borrow flag, integer overflow trap, saturation or vxsat change. VRSUB reverses the subtraction direction.
Require RV32/RV64 V 1.0, enabled vector state, vill=0 and supported vtype/SEW. v0.t means vm=0; omission means vm=1. Only mask-enabled vstart<=i<vl elements compute; prestart stays unchanged, inactive/tail follow vma/vta, retaining or all ones; masked vd excludes v0. vstart>=vl (including vl=0) leaves vd unchanged; v0 cannot supply both EEW=1 mask and data. Success resets vstart=0.
Common Usage Scenarios
Element-wise vector differences
Assume enabled V/VS, valid m1,tu,mu, VLEN=4096, vl=4, vstart=0, v0.mask[0..3]=1101; SEW=8, v12=[0,1,255,7], v4=[1,1,1,1]. v8[0]=255, v8[1]=0, v8[3]=6. Lane2 and tails keep old values; vxsat stays unchanged. Success resets vstart=0.
Vector data subtraction
Assume enabled V/VS, valid m1,tu,mu, VLEN=4096, vl=4, vstart=0, v0.mask[0..3]=1101; SEW=8, v12=[0,1,255,7], v4=[1,1,1,1]. v8[0]=255, v8[1]=0, v8[3]=6. Lane2 and tails keep old values; vxsat stays unchanged. Success resets vstart=0.
Pre-Use Checklist
Syntax Check
- vd/vs2/vs1 are aligned EEW=SEW, EMUL=LMUL groups. Equal-width source/destination overlap is legal; equal sources read equal values. vs1[i] is the subtrahend.
- 32-bit OP-V: opcode=1010111, funct6=000010, funct3=000; vm at bit25, vs2 at bits24:20, vs1 at bits19:15, vd at bits11:7.
Semantic Check
- Active vd[i]=(vs2[i] - vs1[i]) mod 2^SEW, without a borrow flag, integer overflow trap, saturation or vxsat change. VRSUB reverses the subtraction direction.
- Require RV32/RV64 V 1.0, enabled vector state, vill=0 and supported vtype/SEW. v0.t means vm=0; omission means vm=1. Only mask-enabled vstart<=i<vl elements compute; prestart stays unchanged, inactive/tail follow vma/vta, retaining or all ones; masked vd excludes v0. vstart>=vl (including vl=0) leaves vd unchanged; v0 cannot supply both EEW=1 mask and data. Success resets vstart=0.
Pitfalls / Common Confusions
The result wraps at SEW width and does not raise integer overflow exceptions.
Operand order is vs2 - vs1/rs1, not the reverse.
Use vrsub when scalar-minus-vector order is required.
FAQ
Does VSUB.VV trap on underflow?
No. Ordinary vector integer subtraction keeps the low SEW bits, so the result wraps at SEW width.