Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VSUB.VV
RISC-V VSUB.VV Instruction Details
Instruction ManualOPIVVElement-wise vector integer subtraction.
Instruction Syntax
vsub.vv vd, vs2, vs1, vm
Operand Breakdown
vs3: source vector register group providing active elements to store.
rs1: integer base-address register; unit-stride forms write consecutive addresses.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector Operations
Instruction Behavior
VSUB.VV computes vs2[i] - vs1[i] for active elements and writes the low SEW bits to vd.
VSUB.VV Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VSUB subtracts the second source from vs2, wraps at SEW, and writes vd.
Instruction input
vsub.vv
OP-V encodingvsub.vv
funct6
000010
vm
0
vs2
01000
vs1
01100
funct3
000
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x00fa
0x010b
0x011c
0x012d
0x013e
0x014f
0x0160
0x0171
-
-
-
-
-
-
-
-
v12
0x000d
0x0016
0x001f
0x0028
0x0031
0x003a
0x0043
0x004c
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vsub.vv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer subtraction, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VSUB.VV computes vs2[i] - vs1[i] element by element. The low SEW bits are kept; subtraction underflow wraps modulo 2^SEW and raises no integer exception.
This page follows the official RISC-V V extension: vector instructions operate on body elements within the current vl. Unmasked forms operate on all body elements; forms with vm use v0 as the execution mask when vm=0. SEW, LMUL, tail policy, and mask policy come from the current vtype, usually set by vsetvli, vsetivli, or vsetvl.
VSUB is single-width integer subtraction; vector operands have EEW=SEW.
The `.vv` operand order is vd, vs2, vs1; the subtraction direction is vs2 minus vs1.
In OP-V encoding, opcode=1010111 and VSUB uses funct6=000010; the `.vv` form is selected by funct3=000.
The result wraps to the low SEW bits and provides no borrow flag or overflow trap.
Vector Execution Context
When reading VSUB.VV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vv: two vector sources participate element by element.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «vsub.vv v1, v2, v3 # v1[i] = v2[i] - v3[i]».
Data Storing
Understand this scenario with real code like «vsub.vv v1, v2, v3 # v1[i] = v2[i] - v3[i]».
Vector Operations
Understand this scenario with real code like «vsub.vv v1, v2, v3 # v1[i] = v2[i] - v3[i]».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is OPIVV.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
The result wraps at SEW width and does not raise integer overflow exceptions.
Operand order is vs2 - vs1/rs1, not the reverse.
Use vrsub when scalar-minus-vector order is required.
FAQ
How is VSUB.VV different from VRSUB?
VSUB.VV subtracts in the vs2[i] - vs1[i] direction. VRSUB is reverse subtraction: scalar or immediate minus vs2[i].
Does VSUB.VV trap on underflow?
No. Ordinary vector integer subtraction keeps the low SEW bits, so the result wraps at SEW width.