What is the operand direction of VSUB.VV?
It is vs2 minus the second operand, unlike the reverse-subtract direction of VRSUB.
VSUB.VV
RISC-V VSUB.VV Instruction Details
Instruction ManualR-typeElement-wise vector integer subtraction.
Instruction Syntax
vsub.vv vd, vs2, vs1, vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
VVector Operations
Related Search Terms
Instruction Behavior
VSUB.VV computes vs2[i] - vs1[i] for active elements and writes the low SEW bits to vd.
Quick Understanding & Search Notes
VSUB.VV is ordinary vector integer subtraction with results wrapping at SEW width.
Integer overflow does not raise an exception.
VX uses a scalar integer register as the second operand; VV uses vector elements.
Use VRSUB, not VSUB, when you need scalar minus vector.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «vsub.vv v8, v12, v4, v0.t».
Data Storing
Understand this scenario with real code like «vsub.vv v8, v12, v4, v0.t».
Vector Operations
Understand this scenario with real code like «vsub.vv v8, v12, v4, v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
The result wraps at SEW width and does not raise integer overflow exceptions.
Operand order is vs2 - vs1/rs1, not the reverse.
Use vrsub when scalar-minus-vector order is required.