Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VADD.VV
RISC-V VADD.VV Instruction Details
Instruction ManualR-typeAdd integer elements: vd[i] = vs2[i] + vs1[i].
Instruction Syntax
vadd.vv vd, vs2, vs1, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector OperationsInteger Arithmetic
Instruction Behavior
VADD.VV performs RVV single-width integer addition. Each active element computes vd[i] = vs2[i] + vs1[i], writes the low SEW bits, and wraps on integer overflow without trapping. With vm=0, v0 is the execution mask; body elements whose mask bit is 0 do not execute this add, and their destination elements follow the current mask policy.
VADD.VV Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VADD single-width integer add reads active elements, wraps at SEW, and writes vd.
Instruction input
vadd.vv
OP-V encodingvadd.vv
funct6
000000
vm
0
vs2
01000
vs1
01100
funct3
000
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x00fa
0x010b
0x011c
0x012d
0x013e
0x014f
0x0160
0x0171
+
+
+
+
+
+
+
+
v12
0x000d
0x0016
0x001f
0x0028
0x0031
0x003a
0x0043
0x004c
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vadd.vv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer addition, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VADD.VV performs ordinary integer addition element by element from two vector sources. Active elements read vs2[i] and vs1[i], write the low SEW result, and masked forms use v0.t to decide which body elements participate.
VADD uses OP-V vector-arithmetic encoding with funct6=000000; the .vv form is selected by funct3=000.
All vector operands have EEW=SEW, and register-group size follows the current LMUL.
Only body elements within the current vl are processed; vm=0 uses the v0 mask, vm=1 is unmasked, and masked-off destination elements follow the current mask policy.
Integer overflow keeps the low SEW bits and sets no integer or floating-point exception flag; use VSADD/VSADDU for saturating semantics.
Vector Execution Context
When reading VADD.VV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vv: two vector sources participate element by element.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Vectorized Loops
Understand this scenario with real code like «vadd.vv v1, v2, v3, v0.t # masked: v1[i] = v2[i] + v3[i]».
Array Ops
Understand this scenario with real code like «vadd.vv v1, v2, v3, v0.t # masked: v1[i] = v2[i] + v3[i]».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
VADD.VV is ordinary single-width integer add and keeps the low SEW bits; it is not saturating add.
With vm=0, only body elements whose v0 mask bit is 1 execute this add; masked-off destination elements follow the current mask policy.
Both vs2 and vs1 are vector sources interpreted with the current SEW/LMUL; no integer scalar register is read.
FAQ
How do I choose VADD.VV, VADD.VX, and VADD.VI?
Use .vv when both operands are vector registers, .vx when one operand is an integer scalar register, and .vi for a small 5-bit signed constant.
Does VADD saturate or set an overflow flag?
No. VADD is ordinary two's-complement addition and keeps the low SEW bits. Saturating add is a separate RVV instruction category.