Check vl first
Body elements satisfy vstart ≤ i < vl; vstart≥vl leaves the destination unchanged. Set supported vl/vtype and initialize the sources and v0 first.
VADD.VI
RISC-V VADD.VI Instruction Details
Instruction ManualOP-VAdd active body elements at single width, retaining the low SEW result bits.
Instruction Syntax
vadd.vi vd, vs2, imm[, v0.t]
Operand Breakdown
vd and vs2 are SEW-wide vector register groups; equal vector sources read identical initial elements, and same-EEW destination/source overlap is permitted.
imm is a signed 5-bit value (-16..15), sign-extended to SEW.
Omitting the mask means vm=1; v0.t means vm=0, with execution only where the body element's mask bit is 1.
Require V and the selected vtype. Body elements satisfy vstart ≤ i < vl; results wrap at SEW and tails follow vta. v0 cannot be read at both EEW=1 and SEW; masked vd cannot overwrite v0.
VVector OperationsInteger Arithmetic
Instruction Behavior
VADD.VI performs RVV single-width integer addition on active elements: vd[i] = vs2[i] + sign_extend(imm). imm is a 5-bit signed immediate (-16..15), sign-extended to SEW; the low SEW bits are written back and integer overflow wraps at SEW width. With vm=0, body elements whose mask bit is 0 do not execute this add, and their destination elements follow the current mask policy. Requires V 1.0 and support for the selected vtype on RV32/RV64. Body elements satisfy vstart ≤ i < vl; vstart≥vl leaves the destination unchanged. Tails follow vta.
VADD.VI Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VADD single-width integer add reads active elements, wraps at SEW, and writes vd.
Instruction input
vadd.vi
Require valid vtype, enabled VS, and supported SEW; VL=0 updates nothing, including tails. Steps are teaching stages, not processor cycles.
Execution Context
immediate value
-3 -> 0xfffd
5-bit signed imm is sign-extended to SEWThe teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. It fixes VLEN=4096, VLMAX=4096/16=256, and assumes support for the selected SEW; equal vector sources require equal elements. In ordinary masked forms, inactive and tail elements follow vtype.vma/vta and the result row does not invent a definite value; VADC/VMADC/VSBC/VMSBC execute every body element, with v0 bits used only as carry/borrow-in.
OP-V encodingvadd.vi
funct6
000000
vm
0
vs2
01000
simm5
11101
funct3
011
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x00fa
0x010b
0x011c
0x012d
0x013e
0x014f
0x0160
0x0171
+
+
+
+
+
+
+
+
imm
0xfffd
0xfffd
0xfffd
0xfffd
0xfffd
0xfffd
0xfffd
0xfffd
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vadd.vi uses OP-V encoding. The animation places fixed fields, register fields, vm, and the imm field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer addition, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VADD.VI adds a 5-bit signed immediate to each active element of vs2. The immediate is sign-extended to SEW, so this form is for small constants in the -16..15 range.
VADD uses OP-V vector-arithmetic encoding with funct6=000000; the .vi form is selected by funct3=011.
The immediate field is a 5-bit signed value, giving assembly range -16..15, and is sign-extended to SEW.
Only body elements within the current vl are processed; vm=0 uses the v0 mask, vm=1 is unmasked, and masked-off destination elements follow the current mask policy.
Ordinary integer addition wraps at SEW width without saturation; VSADD/VSADDU provide saturating add.
Vector Execution Context
When reading VADD.VI, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vi: one vector source and a small immediate participate.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
With vm=0, v0.t selects active body elements; omitting the mask operand means vm=1, unmasked. Inactive and tail elements follow current vma/vta.
Common Usage Scenarios
Vectorized Loops
Assume V with e8,m1, vl=4, vstart=0, all vs2 elements=255, imm=-1, and v0 bits 1010 in lane order 0..3. The example vadd.vi v1, v2, -1, v0.t gives [254,policy,254,policy]; policy marks inactive elements governed by vma, without a definite value, and tails follow vta.
Array Ops
Assume V with e8,m1, vl=4, vstart=0, all vs2 elements=255, imm=-1, and v0 bits 1010 in lane order 0..3. The example vadd.vi v1, v2, -1, v0.t gives [254,policy,254,policy]; policy marks inactive elements governed by vma, without a definite value, and tails follow vta.
Pre-Use Checklist
Syntax Check
- vd and vs2 are SEW-wide vector register groups; equal vector sources read identical initial elements, and same-EEW destination/source overlap is permitted.
- imm is a signed 5-bit value (-16..15), sign-extended to SEW.
Semantic Check
- Omitting the mask means vm=1; v0.t means vm=0, with execution only where the body element's mask bit is 1.
- Require V and the selected vtype. Body elements satisfy vstart ≤ i < vl; results wrap at SEW and tails follow vta. v0 cannot be read at both EEW=1 and SEW; masked vd cannot overwrite v0.
Pitfalls / Common Confusions
imm is a 5-bit signed immediate with range -16..15; it is not an arbitrary-width constant.
The immediate is sign-extended to SEW before ordinary integer addition with each active element.
The result keeps the low SEW bits and does not saturate; use vadd.vx for larger constants.
Masked vd cannot overlap v0; v0 cannot also be a SEW data source. Equal vector sources read identical initial elements.
FAQ
How do I choose VADD.VV, VADD.VX, and VADD.VI?
Use .vv when both operands are vector registers, .vx when one operand is an integer scalar register, and .vi for a small 5-bit signed constant.
Does VADD saturate or set an overflow flag?
No. VADD is ordinary two's-complement addition and keeps the low SEW bits. Saturating add is a separate RVV instruction category.