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VADD.VI

RISC-V VADD.VI Instruction Details

Instruction ManualR-type

Add each vs2 element with imm: vd[i]=vs2[i]+imm.

Instruction Syntax

vadd.vi vd, vs2, imm, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector OperationsInteger Arithmetic
Related Search Terms
VADD.VI instructionRISC-V VADD.VIvadd.vi syntaxvadd.vi encodingvadd.vi immediateRVV immediate addVADD.VI range

Instruction Behavior

VADD.VI performs RVV single-width integer addition on active elements: vd[i] = vs2[i] + sign_extend(imm). imm is a 5-bit signed immediate (-16..15), sign-extended to SEW; the low SEW bits are written back and integer overflow wraps at SEW width. With vm=0, body elements whose mask bit is 0 do not execute this add, and their destination elements follow the current mask policy.

VADD.VI Decode And Execute Animation

Starts from OP-V encoding fields, then shows how VADD single-width integer add reads active elements, wraps at SEW, and writes vd.

Instruction input
vadd.vi
immediate value
-3 -> 0xfffd
5-bit signed imm is sign-extended to SEW
OP-V encodingvadd.vi
funct6
000000
vm
0
vs2
01000
simm5
11101
funct3
011
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x00fa
0x010b
0x011c
0x012d
0x013e
0x014f
0x0160
0x0171
+
+
+
+
+
+
+
+
imm
0xfffd
0xfffd
0xfffd
0xfffd
0xfffd
0xfffd
0xfffd
0xfffd
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step

Show OP-V 32-bit encoding fields

vadd.vi uses OP-V encoding. The animation places fixed fields, register fields, vm, and the imm field in one encoding strip.

This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer addition, mask control, and vd writeback. It does not model pipelines, caches, or timing.

Quick Understanding & Search Notes

VADD.VI adds a 5-bit signed immediate to each active element of vs2. The immediate is sign-extended to SEW, so this form is for small constants in the -16..15 range.

VADD uses OP-V vector-arithmetic encoding with funct6=000000; the .vi form is selected by funct3=011.
The immediate field is a 5-bit signed value, giving assembly range -16..15, and is sign-extended to SEW.
Only body elements within the current vl are processed; vm=0 uses the v0 mask, vm=1 is unmasked, and masked-off destination elements follow the current mask policy.
Integer overflow keeps the low SEW bits and sets no integer or floating-point exception flag; use VSADD/VSADDU for saturating semantics.
RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations

Vector Execution Context

When reading VADD.VI, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vi: one vector source and a small immediate participate.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Vectorized Loops

Understand this scenario with real code like «vadd.vi v1, v2, -1 # add small signed immediate to each active element».

Array Ops

Understand this scenario with real code like «vadd.vi v1, v2, -1 # add small signed immediate to each active element».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

imm is a 5-bit signed immediate with range -16..15; it is not an arbitrary-width constant.
The immediate is sign-extended to SEW before ordinary integer addition with each active element.
The result keeps the low SEW bits and does not saturate; use vadd.vx for larger constants.

FAQ

How do I choose VADD.VV, VADD.VX, and VADD.VI?

Use .vv when both operands are vector registers, .vx when one operand is an integer scalar register, and .vi for a small 5-bit signed constant.

Does VADD saturate or set an overflow flag?

No. VADD is ordinary two's-complement addition and keeps the low SEW bits. Saturating add is a separate RVV instruction category.