Does it use vxrm rounding?
No. VADD.VI is ordinary integer addition; vxrm is for fixed-point rounding instructions.
VADD.VI
RISC-V VADD.VI Instruction Details
Instruction ManualR-typeAdd each vs2 element with imm: vd[i]=vs2[i]+imm.
Instruction Syntax
vadd.vi vd, vs2, imm, vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
VVector OperationsInteger Arithmetic
Instruction Behavior
VADD.VI performs ordinary vector integer addition on active elements: vd[i] = vs2[i] + sign_extend(imm). imm is a 5-bit signed immediate (-16..15), sign-extended to SEW. The result wraps at SEW width; this is not saturating add and does not use vxrm rounding.
Quick Understanding & Search Notes
VADD.VI performs ordinary integer addition for each active element. The second operand is a 5-bit immediate sign-extended to SEW, and the result is written at SEW width.
The immediate range is -16 to 15; larger constants are usually placed in an integer register and used with vadd.vx.
Ordinary vector integer add is not saturating; overflow wraps at SEW width.
Common Usage Scenarios
Vectorized Loops
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vadd.vi v1, v2, 5».
Array Ops
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vadd.vi v1, v2, 5».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
imm is a 5-bit signed immediate (-16..15), sign-extended to SEW.
Ordinary integer addition wraps at SEW width; it is not saturating add.
Use vadd.vx when a larger constant is needed.
FAQ
How wide is imm?
imm is a 5-bit signed immediate, sign-extended to the current SEW.