Can VMV.V.I take v0.t?
No. VMV.V is an unmasked move form; use VMERGE when conditional selection under v0 is required.
VMV.V.I
RISC-V VMV.V.I Instruction Details
Instruction ManualOPIVIBroadcasts 5-bit signed immediate to vd body elements as an unmasked vector move.
Instruction Syntax
vmv.v.i vd, imm
Operand Breakdown
vd is a vector group at current LMUL; imm is a signed 5-bit immediate, −16…15, sign-extended to SEW.
32-bit OP-V: opcode=1010111, funct6=010111, funct3=011, vm=1, vs2=00000; no v0.t operand.
Every body element vstart≤i<vl receives the immediate; v0 bits and vma do not select body elements. Tails follow vta: preserve old values or permit all ones.
vstart≥vl (including vl=0) updates no destination elements; successful completion resets vstart to 0. Require V 1.0, valid supported vtype and non-Off mstatus.VS; with H and virtualization V=1, vsstatus.VS must also be non-Off.
VVector Data MovementScalar-Vector Transfer
Instruction Behavior
VMV.V.I is an unmasked immediate broadcast in RISC-V V. It sign-extends a signed 5-bit immediate (−16…15) to SEW and writes every body element vstart≤i<vl. Prestart is preserved and tails follow vtype.vta. The encoding fixes vm=1 and vs2=00000; v0.t is not accepted.
VMV.V.I Decode And Execute Animation
Starts from OP-V encoding fields, then shows how the unmasked VMV.V move form writes the current source value into vd body elements.
Instruction input
vmv.v.i
Require valid vtype, enabled VS, and supported SEW; VL=0 updates nothing, including tails. An ordinary masked vd cannot be v0; v0 cannot supply both mask and SEW data. Same-width source/destination overlap is legal. Steps are teaching stages, not processor cycles.
Execution Context
immediate value
-3 -> 0xfffd
5-bit signed imm is sign-extended to SEWThe teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. It fixes VLEN=4096, VLMAX=4096/16=256, and assumes support for the selected SEW; equal vector sources require equal elements. VMV.V.I fixes vm=1 and vs2=0; every body element receives the sign-extended immediate. Tails follow vtype.vta; vma does not affect this unmasked form.
OP-V encodingvmv.v.i
funct6
010111
vm
1
vs2
00000
simm5
11101
funct3
011
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
copy
copy
copy
copy
copy
copy
copy
copy
imm
0xfffd
0xfffd
0xfffd
0xfffd
0xfffd
0xfffd
0xfffd
0xfffd
active
1
1
1
1
1
1
1
1
v4
...
...
...
...
...
...
...
...
Current step
Show OP-V 32-bit encoding fields
vmv.v.i uses OP-V encoding. The animation places fixed fields, register fields, vm, and the imm field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer broadcast, fixed unmasked move, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VMV.V.I is an unmasked VMV.V immediate broadcast form that sign-extends the 5-bit signed immediate to SEW and broadcasts it to vd body elements. It performs no arithmetic and no memory access.
Body elements satisfy vstart≤i<vl; prestart is preserved, tails follow vtype.vta (old values or permitted all ones), and vma does not affect this unmasked form.
VMV.V is an unmasked move form with encoding vm=1 and vs2=v0.
The source operand is 5-bit signed immediate; the result is broadcast to vd body elements within the current vl.
VMV.V performs no arithmetic, reads no memory, and does not use v0.t to select a subset of body elements.
Require V 1.0, supported SEW/LMUL, vtype.vill=0 and non-Off mstatus.VS; with H and virtualization V=1, vsstatus.VS must also be non-Off. vstart≥vl (including vl=0) updates no destination elements, including tails.
OP-V opcode=1010111, funct6=010111, funct3=011; imm[4:0] occupies bits 19:15 and ranges from −16 to 15.
Vector Execution Context
vd is a vector group at current LMUL; imm is a signed 5-bit immediate, −16…15, sign-extended to SEW.
32-bit OP-V: opcode=1010111, funct6=010111, funct3=011, vm=1, vs2=00000; no v0.t operand.
Every body element vstart≤i<vl receives the immediate; v0 bits and vma do not select body elements. Tails follow vta: preserve old values or permit all ones.
vstart≥vl (including vl=0) updates no destination elements; successful completion resets vstart to 0. Require V 1.0, valid supported vtype and non-Off mstatus.VS; with H and virtualization V=1, vsstatus.VS must also be non-Off.
Common Usage Scenarios
Vector Init
Assume enabled V/VS, valid e8,m1, VLEN≥128, vl=4 and vstart=0; imm=−3 → v4[0..3]=[0xfd,0xfd,0xfd,0xfd]. Tails follow vta. Tails are not assumed zero; vl=0 leaves the whole destination unchanged.
Vector Constant Setup
Assume enabled V/VS, valid e8,m1, VLEN≥128, vl=4 and vstart=0; imm=−3 → v4[0..3]=[0xfd,0xfd,0xfd,0xfd]. Tails follow vta. Tails are not assumed zero; vl=0 leaves the whole destination unchanged.
Pre-Use Checklist
Syntax Check
- vd is a vector group at current LMUL; imm is a signed 5-bit immediate, −16…15, sign-extended to SEW.
- 32-bit OP-V: opcode=1010111, funct6=010111, funct3=011, vm=1, vs2=00000; no v0.t operand.
Semantic Check
- Every body element vstart≤i<vl receives the immediate; v0 bits and vma do not select body elements. Tails follow vta: preserve old values or permit all ones.
- vstart≥vl (including vl=0) updates no destination elements; successful completion resets vstart to 0. Require V 1.0, valid supported vtype and non-Off mstatus.VS; with H and virtualization V=1, vsstatus.VS must also be non-Off.
Pitfalls / Common Confusions
VMV.V is an unmasked move form, and the syntax has no v0.t.
The encoding fixes vs2=v0 and vm=1; do not interpret it as conditional execution under v0.
Tail elements still follow the current tail policy.
FAQ
Does VMV.V.I access memory or perform arithmetic?
No. It only broadcasts bit patterns through registers and current body elements.