Which source does v0 bit 1 select in VMERGE.VIM?
v0[i]=1 selects the signed 5-bit immediate; v0[i]=0 selects vs2[i].
VMERGE.VIM
RISC-V VMERGE.VIM Instruction Details
Instruction ManualOPIVISelect element-wise between vs2 and a 5-bit signed immediate using v0 selection mask bits, writing vd.
Instruction Syntax
vmerge.vim vd, vs2, imm, v0
Operand Breakdown
v0[i]=0 selects vs2[i]; v0[i]=1 selects the second source. Fixed vm=0 uses v0 as selection data, and every body element is written.
32-bit OP-V: opcode=1010111, funct6=010111, funct3=011. imm is -16..15, sign-extended to SEW.
Same-EEW sources/destination may overlap; vd cannot cover v0, and v0 cannot supply both EEW=1 selection bits and SEW data.
Require valid vtype, enabled VS, and supported SEW. VMV instead uses vm=1 and vs2=v0; distinguish it from VMERGE.
Body is vstart≤i<vl; prestart is unchanged, tails follow vta. VL=0 or vstart≥vl updates no destination, including tails. The animation fixes LMUL=m1, VLEN=4096, vstart=0; steps are not processor cycles.
VVector Data MovementMerge/Select
Instruction Behavior
VMERGE.VIM is a RISC-V V vector integer merge instruction. v0.mask[i]=0 selects vs2[i], and v0.mask[i]=1 selects the 5-bit immediate sign-extended to SEW.
VMERGE.VIM Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VMERGE uses v0 as selection data: bit 0 selects vs2, bit 1 selects the second source, and every body element is written.
Instruction input
vmerge.vim
v0
v0
selection-mask data, vm=0Require valid vtype, enabled VS, and supported SEW. Only body elements are shown; VL=0 updates no destination elements, including tails. Same-EEW sources/destination may overlap. When v0 supplies EEW=1 mask/selection bits, it cannot also supply SEW data or be vd.
Execution Context
immediate value
-3 -> 0xfffd
5-bit signed imm is sign-extended to SEWThe teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. It fixes VLEN=4096, VLMAX=4096/16=256, and assumes support for the selected SEW; equal vector sources require equal elements. VMERGE fixes vm=0; each v0 bit selects one of two sources, every body element executes, and only tails follow vtype.vta.
OP-V encodingvmerge.vim
funct6
010111
vm
0
vs2
01000
simm5
11101
funct3
011
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x0020
0x0027
0x002e
0x0035
0x003c
0x0043
0x004a
0x0051
select
select
select
select
select
select
select
select
imm
0xfffd
0xfffd
0xfffd
0xfffd
0xfffd
0xfffd
0xfffd
0xfffd
v0
1
0
1
1
1
0
1
1
v4
...
...
...
...
...
...
...
...
Current step
Show OP-V 32-bit encoding fields
vmerge.vim uses OP-V encoding. The animation places fixed fields, register fields, vm, and the imm field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer v0-selected merge, v0 selection data, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VMERGE.VIM: v0 bit 0 selects vs2; bit 1 selects a signed 5-bit immediate. Every body element receives its selected value.
Body: vstart≤i<vl. Prestart stays unchanged; tails follow vta. VL=0 or vstart≥vl leaves every destination unchanged.
imm is -16..15 and sign-extended to SEW; v0[i]=0 selects vs2[i], while v0[i]=1 selects the extended immediate.
OP-V: opcode=1010111, funct6=010111, funct3=011, vm=0. VMV instead uses vm=1 and vs2=v0.
Require valid vtype, enabled VS and supported SEW. Same-EEW overlap is legal. vd cannot be v0; v0 cannot supply both SEW data and EEW=1 selection bits.
Vector Execution Context
v0[i]=0 selects vs2[i]; v0[i]=1 selects the second source. Fixed vm=0 uses v0 as selection data, and every body element is written.
32-bit OP-V: opcode=1010111, funct6=010111, funct3=011. imm is -16..15, sign-extended to SEW.
Same-EEW sources/destination may overlap; vd cannot cover v0, and v0 cannot supply both EEW=1 selection bits and SEW data.
Require valid vtype, enabled VS, and supported SEW. VMV instead uses vm=1 and vs2=v0; distinguish it from VMERGE.
Body is vstart≤i<vl; prestart is unchanged, tails follow vta. VL=0 or vstart≥vl updates no destination, including tails. The animation fixes LMUL=m1, VLEN=4096, vstart=0; steps are not processor cycles.
Common Usage Scenarios
Mask Widening
Assume enabled V/VS, supported e32,m1, VLEN≥128, vl=4, vstart=0, ta/ma, and initialized sources; Fixed vm=0 selects at every body element. v4=[10,20,30,40], imm=7, v0.mask=[1,0,1,1] → v8=[7,20,7,7]. Tails are not guaranteed zero; mask destinations are always tail-agnostic.
Conditional Assignment
Assume enabled V/VS, supported e32,m1, VLEN≥128, vl=4, vstart=0, ta/ma, and initialized sources; Fixed vm=0 selects at every body element. v4=[10,20,30,40], imm=7, v0.mask=[1,0,1,1] → v8=[7,20,7,7]. Tails are not guaranteed zero; mask destinations are always tail-agnostic.
Pre-Use Checklist
Syntax Check
- v0[i]=0 selects vs2[i]; v0[i]=1 selects the second source. Fixed vm=0 uses v0 as selection data, and every body element is written.
- 32-bit OP-V: opcode=1010111, funct6=010111, funct3=011. imm is -16..15, sign-extended to SEW.
Semantic Check
- Same-EEW sources/destination may overlap; vd cannot cover v0, and v0 cannot supply both EEW=1 selection bits and SEW data.
- Require valid vtype, enabled VS, and supported SEW. VMV instead uses vm=1 and vs2=v0; distinguish it from VMERGE.
- Body is vstart≤i<vl; prestart is unchanged, tails follow vta. VL=0 or vstart≥vl updates no destination, including tails. The animation fixes LMUL=m1, VLEN=4096, vstart=0; steps are not processor cycles.
Pitfalls / Common Confusions
v0 is selection data, not the ordinary v0.t execution mask.
A v0 bit of 0 selects vs2, and a bit of 1 selects the second source.
VMERGE and VMV share related encoding space, but their semantics are selected merge versus unmasked move.
FAQ
Is VMERGE an ordinary masked instruction?
No. v0 selects between two sources for every body element; it does not disable execution.