What format does VMSEQ.VI produce?
The result is written in mask-register layout, one predicate bit per active element, not ordinary SEW-wide vector elements such as 0/1 or 0/-1.
VMSEQ.VI
RISC-V VMSEQ.VI Instruction Details
Instruction ManualOPIVIVMSEQ.VI performs element-wise equality immediate comparison and writes active-element Boolean results to the destination mask.
Instruction Syntax
vmseq.vi vd, vs2, imm[, v0.t]
Operand Breakdown
Syntax: vmseq.vi vd, vs2, imm[, v0.t]; vd is a one-bit-per-element mask and data sources are read at SEW.
32-bit OP-V: opcode=1010111, funct6=011000, funct3=011 (OPIVI). Omitting v0.t gives vm=1; including it gives vm=0.
Active elements compare vs2[i] with simm5 (-16..15), sign-extended to SEW: matching bits write 1, otherwise 0. Equality does not distinguish signed from unsigned.
The mask destination may be v0. Overlap with a SEW source must start at the source group's lowest register; legal different-EEW overlap forces ma/ta. With m1, equal register names are legal. When v0 supplies mask/borrow bits, it cannot also supply SEW data.
Require RV32/RV64 V 1.0, valid vtype, enabled VS, and supported SEW; body is vstart≤i<vl and prestart is unchanged. Inactive elements follow vma; mask tails are always agnostic. VL=0 updates no destination, including tails. The animation shows only body elements in a fixed legal configuration; steps are not processor cycles.
VVector IntegerCompare
Instruction Behavior
VMSEQ.VI is a RISC-V V-extension vector-immediate integer predicate-generation instruction. Within the current vl body elements, it compares vs2[i] with the sign-extended 5-bit immediate; vm=1 lets all body elements participate, while vm=0 processes only elements selected by v0.t. The result is written to vd in mask-register layout, one bit per element index; integer compares do not set floating-point exception flags.
VMSEQ.VI Decode And Execute Animation
Starts from OP-V encoding, then shows how integer equal with immediate comparison reads active elements and produces a one-bit-per-element predicate mask.
Instruction input
vmseq.vi
Execution context
Fixed legal teaching context: VLEN=4096 bits, LMUL=m1, and vstart=0; every selectable VL is within VLMAX=128 for the current SEW.
immediate value
7 -> 7
5-bit signed imm is sign-extended to SEWRequire valid vtype, enabled VS, and supported SEW. The destination may be v0 and, with LMUL=m1, may equal a data source. Equal data sources require equal elements; under v0.t, v0 cannot also be read as SEW data. Result tails are always agnostic; masked-off values follow vma. VL=0 updates nothing, including tails.
Legal destination overlap with a SEW data source forces ma/ta; steps are teaching stages, not processor cycles.
V-format integer compare encoding
31..26
funct6
011000
25
vm
1
24..20
vs2
v8
19..15
imm
00111 (7)
14..12
funct3
011
11..7
vd
v0
6..0
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
3
2
7
7
0
12
5
9
==
==
==
==
==
==
==
==
==
imm
7
7
7
7
7
7
7
7
active
1
1
1
1
1
1
1
1
v0
-
-
-
-
-
-
-
-
This animation shows only the ISA-visible comparison, execution-mask, and destination-mask writeback relationship with vstart fixed at 0; inactive and tail elements are not simulated as fixed data values. For .vx, the selectable SEW values (8/16/32) do not exceed XLEN, so the model first takes the low SEW bits of x[rs1] and then applies this instruction's signed or unsigned relation.
Quick Understanding & Search Notes
VMSEQ.VI does not write an ordinary integer vector; it writes each active element's equality immediate comparison result as one bit of the destination mask. The animation starts from OP-V encoding fields, decodes the vector-immediate operands, then shows per-lane comparison and vd.mask writeback.
Active body elements write vd.mask[i] = (vs2[i] == sign-extended simm5).
OP-V opcode=1010111; funct3 selects OPIVI; funct6 selects equality.
simm5 is -16..15, sign-extended to SEW; at SEW=8, -1 and 255 have equal bit patterns.
vm=0 selects active elements with v0.t; vm=1 is unmasked. Inactive and tail values are not fixed in the animation.
Mask tails are always agnostic; VL=0 updates nothing, including tails. With LMUL=m1, vd may equal a data source. With vm=0, v0 cannot also supply SEW data. Legal different-EEW destination/source overlap forces ma/ta.
Vector Execution Context
Syntax: vmseq.vi vd, vs2, imm[, v0.t]; vd is a one-bit-per-element mask and data sources are read at SEW.
32-bit OP-V: opcode=1010111, funct6=011000, funct3=011 (OPIVI). Omitting v0.t gives vm=1; including it gives vm=0.
Active elements compare vs2[i] with simm5 (-16..15), sign-extended to SEW: matching bits write 1, otherwise 0. Equality does not distinguish signed from unsigned.
The mask destination may be v0. Overlap with a SEW source must start at the source group's lowest register; legal different-EEW overlap forces ma/ta. With m1, equal register names are legal. When v0 supplies mask/borrow bits, it cannot also supply SEW data.
Require RV32/RV64 V 1.0, valid vtype, enabled VS, and supported SEW; body is vstart≤i<vl and prestart is unchanged. Inactive elements follow vma; mask tails are always agnostic. VL=0 updates no destination, including tails. The animation shows only body elements in a fixed legal configuration; steps are not processor cycles.
Common Usage Scenarios
Conditional Execution
Assume RV32/RV64 V 1.0, enabled VS, valid e32,m1, VLEN≥128, vl=4, vstart=0, and initialized sources; The example is unmasked. v2=[0,1,0xffffffff,0], imm=0 → v1.mask[0..3]=[1,0,0,1]. Only mask bits are written; tails are always agnostic without assumed zeroing.
Range Check
Assume RV32/RV64 V 1.0, enabled VS, valid e32,m1, VLEN≥128, vl=4, vstart=0, and initialized sources; The example is unmasked. v2=[0,1,0xffffffff,0], imm=0 → v1.mask[0..3]=[1,0,0,1]. Only mask bits are written; tails are always agnostic without assumed zeroing.
Pre-Use Checklist
Syntax Check
- Syntax: vmseq.vi vd, vs2, imm[, v0.t]; vd is a one-bit-per-element mask and data sources are read at SEW.
- 32-bit OP-V: opcode=1010111, funct6=011000, funct3=011 (OPIVI). Omitting v0.t gives vm=1; including it gives vm=0.
Semantic Check
- Active elements compare vs2[i] with simm5 (-16..15), sign-extended to SEW: matching bits write 1, otherwise 0. Equality does not distinguish signed from unsigned.
- The mask destination may be v0. Overlap with a SEW source must start at the source group's lowest register; legal different-EEW overlap forces ma/ta. With m1, equal register names are legal. When v0 supplies mask/borrow bits, it cannot also supply SEW data.
- Require RV32/RV64 V 1.0, valid vtype, enabled VS, and supported SEW; body is vstart≤i<vl and prestart is unchanged. Inactive elements follow vma; mask tails are always agnostic. VL=0 updates no destination, including tails. The animation shows only body elements in a fixed legal configuration; steps are not processor cycles.
Pitfalls / Common Confusions
VMSEQ.VI writes vd in mask-register layout, producing one predicate bit per element rather than SEW-wide integer results.
The immediate is -16..15 and is sign-extended to SEW before bit-pattern comparison; equality does not distinguish signed from unsigned.
With vm=0, only body elements selected by v0.t generate new results; mask-off and tail elements should not be taught as definitely writing zero.
FAQ
How does the immediate participate in the compare?
The immediate is -16..15 and is sign-extended to SEW, then compared for equality with the SEW-bit pattern of vs2[i].
Does vm or v0.t change the comparison relation?
No. vm only selects which body elements are active; active elements still use this instruction-specific comparison relation to generate mask bits.