Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VMSEQ.VI
RISC-V VMSEQ.VI Instruction Details
Instruction ManualOPIVIVMSEQ.VI performs element-wise equality immediate comparison and writes active-element Boolean results to the destination mask.
Instruction Syntax
vmseq.vi vd, vs2, imm, vm
Operand Breakdown
vd: mask destination register, with one Boolean result bit per element.
vs2/vs1 or scalar source: compared at the current SEW.
vm: vm=0 uses v0 to restrict participating elements, and vm=1 is unmasked.
VVector IntegerCompare
Instruction Behavior
VMSEQ.VI is a RISC-V V-extension vector-immediate integer predicate-generation instruction. Within the current vl body elements, it compares vs2[i] with the sign-extended 5-bit immediate; vm=1 lets all body elements participate, while vm=0 processes only elements selected by v0.t. The result is written to vd in mask-register layout, one bit per element index; integer compares do not set floating-point exception flags.
VMSEQ.VI Decode And Execute Animation
Starts from OP-V encoding, then shows how integer equal with immediate comparison reads active elements and produces a one-bit-per-element predicate mask.
Instruction input
vmseq.vi
immediate value
7 -> 7
5-bit signed imm is sign-extended to SEWV-format integer compare encoding
31..26
funct6
011000
25
vm
1
24..20
vs2
v8
19..15
imm
00111 (7)
14..12
funct3
011
11..7
vd
v0
6..0
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
3
2
7
7
0
12
5
9
==
==
==
==
==
==
==
==
==
imm
7
7
7
7
7
7
7
7
active
1
1
1
1
1
1
1
1
v0
-
-
-
-
-
-
-
-
This animation shows only the ISA-visible comparison, execution-mask, and destination-mask writeback relationship; inactive and tail elements are not simulated as fixed data values here.
Quick Understanding & Search Notes
VMSEQ.VI does not write an ordinary integer vector; it writes each active element's equality immediate comparison result as one bit of the destination mask. The animation starts from OP-V encoding fields, decodes the vector-immediate operands, then shows per-lane comparison and vd.mask writeback.
The core semantic relation is vd.mask[i] = (vs2[i] == sign-extended simm5); only active body elements generate new destination mask bits.
funct3 selects the OPIVI operand form, funct6 selects the equality immediate relation, and opcode=1010111 is OP-V.
The immediate field is a 5-bit signed imm, sign-extended to SEW first; unsigned relations then interpret the extended SEW bit pattern as unsigned.
vm=0 uses v0.t to select active elements and vm=1 is unmasked; tail and mask-off elements are not forced to concrete values in the animation.
Vector Execution Context
When reading VMSEQ.VI, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vi: one vector source and a small immediate participate.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Conditional Execution
Understand this scenario with real code like «vmseq.vi v1, v2, 0».
Range Check
Understand this scenario with real code like «vmseq.vi v1, v2, 0».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is OPIVI.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
VMSEQ.VI writes vd in mask-register layout, producing one predicate bit per element rather than SEW-wide integer results.
The immediate field is a 5-bit signed value; unsigned compares still sign-extend it to SEW first, then interpret that SEW bit pattern as unsigned.
With vm=0, only body elements selected by v0.t generate new results; mask-off and tail elements should not be taught as definitely writing zero.
FAQ
What format does VMSEQ.VI produce?
The result is written in mask-register layout, one predicate bit per active element, not ordinary SEW-wide vector elements such as 0/1 or 0/-1.
How does the immediate participate in the compare?
The immediate field is a 5-bit signed imm, sign-extended to SEW first; unsigned compares then apply the unsigned relation to that extended SEW bit pattern.
Does vm or v0.t change the comparison relation?
No. vm only selects which body elements are active; active elements still use this instruction-specific comparison relation to generate mask bits.