How are operands compared?
Active elements compare vs2[i] != scalar: true writes 1, false 0. simm5 ranges from -16 to 15 and is sign-extended to SEW before comparing SEW bit patterns for inequality.
VMSNE.VI
RISC-V VMSNE.VI Instruction Details
Instruction ManualOPIVIVMSNE.VI performs element-wise not-equal immediate comparison and writes active-element Boolean results to the destination mask.
Instruction Syntax
vmsne.vi vd, vs2, imm[, v0.t]
Operand Breakdown
Syntax: vmsne.vi vd, vs2, imm[, v0.t]; omit v0.t for vm=1, include it for vm=0. vd is one mask register: bit i corresponds to element i, independent of SEW/LMUL.
32-bit OP-V: opcode=1010111, funct6=011001, funct3=011 (OPIVI).
Active elements compare vs2[i] != scalar: true writes 1, false 0. simm5 ranges from -16 to 15 and is sign-extended to SEW before comparing SEW bit patterns for inequality.
vd may be v0. Destination/data-source overlap must start at the source group’s lowest register and forces ma/ta. With vm=0, v0 cannot also supply SEW data.
Require RV32/RV64 V 1.0, enabled VS, valid vtype and supported SEW. Body is vstart≤i<vl; prestart is unchanged. Inactive follows vma; mask tails are always agnostic. vl=0 updates no destination bits, including tails.
VVector IntegerCompare
Instruction Behavior
VMSNE.VI is a V-extension integer compare instruction. Active elements compare vs2[i] != scalar: true writes 1, false 0. simm5 ranges from -16 to 15 and is sign-extended to SEW before comparing SEW bit patterns for inequality. vm=0 processes only body elements enabled by v0.t; vm=1 is unmasked. The result is a one-bit-per-element mask.
VMSNE.VI Decode And Execute Animation
Starts from OP-V encoding, then shows how integer not equal with immediate comparison reads active elements and produces a one-bit-per-element predicate mask.
Instruction input
vmsne.vi
Execution context
Fixed legal teaching context: VLEN=4096 bits, LMUL=m1, and vstart=0; every selectable VL is within VLMAX=128 for the current SEW.
immediate value
7 -> 7
5-bit signed imm is sign-extended to SEWRequire valid vtype, enabled VS, and supported SEW. The destination may be v0 and, with LMUL=m1, may equal a data source. Equal data sources require equal elements; under v0.t, v0 cannot also be read as SEW data. Result tails are always agnostic; masked-off values follow vma. VL=0 updates nothing, including tails.
Legal destination overlap with a SEW data source forces ma/ta; steps are teaching stages, not processor cycles.
V-format integer compare encoding
31..26
funct6
011001
25
vm
1
24..20
vs2
v8
19..15
imm
00111 (7)
14..12
funct3
011
11..7
vd
v0
6..0
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
3
2
7
7
0
12
5
9
!=
!=
!=
!=
!=
!=
!=
!=
!=
imm
7
7
7
7
7
7
7
7
active
1
1
1
1
1
1
1
1
v0
-
-
-
-
-
-
-
-
This animation shows only the ISA-visible comparison, execution-mask, and destination-mask writeback relationship with vstart fixed at 0; inactive and tail elements are not simulated as fixed data values. For .vx, the selectable SEW values (8/16/32) do not exceed XLEN, so the model first takes the low SEW bits of x[rs1] and then applies this instruction's signed or unsigned relation.
Quick Understanding & Search Notes
Active elements compare vs2[i] != scalar: true writes 1, false 0. Results are mask bits, not SEW-wide integers.
Syntax: vmsne.vi vd, vs2, imm[, v0.t]; omit v0.t for vm=1, include it for vm=0. vd is one mask register: bit i corresponds to element i, independent of SEW/LMUL.
32-bit OP-V: opcode=1010111, funct6=011001, funct3=011 (OPIVI).
Active elements compare vs2[i] != scalar: true writes 1, false 0. simm5 ranges from -16 to 15 and is sign-extended to SEW before comparing SEW bit patterns for inequality.
vd may be v0. Destination/data-source overlap must start at the source group’s lowest register and forces ma/ta. With vm=0, v0 cannot also supply SEW data.
Require RV32/RV64 V 1.0, enabled VS, valid vtype and supported SEW. Body is vstart≤i<vl; prestart is unchanged. Inactive follows vma; mask tails are always agnostic. vl=0 updates no destination bits, including tails.
Vector Execution Context
Syntax: vmsne.vi vd, vs2, imm[, v0.t]; omit v0.t for vm=1, include it for vm=0. vd is one mask register: bit i corresponds to element i, independent of SEW/LMUL.
32-bit OP-V: opcode=1010111, funct6=011001, funct3=011 (OPIVI).
Active elements compare vs2[i] != scalar: true writes 1, false 0. simm5 ranges from -16 to 15 and is sign-extended to SEW before comparing SEW bit patterns for inequality.
vd may be v0. Destination/data-source overlap must start at the source group’s lowest register and forces ma/ta. With vm=0, v0 cannot also supply SEW data.
Require RV32/RV64 V 1.0, enabled VS, valid vtype and supported SEW. Body is vstart≤i<vl; prestart is unchanged. Inactive follows vma; mask tails are always agnostic. vl=0 updates no destination bits, including tails.
Common Usage Scenarios
Integer comparison
Assume RV32/RV64 V 1.0, enabled VS, valid e32,m1, VLEN≥128, vl=4, vstart=0 and initialized sources; the example is unmasked. v2=[0,2,7,9], imm=0 → v1.mask[0..3]=[0,1,1,1]. Only active mask bits are determined; tails are always agnostic without assumed zeroing.
Predicate mask
Assume RV32/RV64 V 1.0, enabled VS, valid e32,m1, VLEN≥128, vl=4, vstart=0 and initialized sources; the example is unmasked. v2=[0,2,7,9], imm=0 → v1.mask[0..3]=[0,1,1,1]. Only active mask bits are determined; tails are always agnostic without assumed zeroing.
Pre-Use Checklist
Syntax Check
- Syntax: vmsne.vi vd, vs2, imm[, v0.t]; omit v0.t for vm=1, include it for vm=0. vd is one mask register: bit i corresponds to element i, independent of SEW/LMUL.
- 32-bit OP-V: opcode=1010111, funct6=011001, funct3=011 (OPIVI).
Semantic Check
- Active elements compare vs2[i] != scalar: true writes 1, false 0. simm5 ranges from -16 to 15 and is sign-extended to SEW before comparing SEW bit patterns for inequality.
- vd may be v0. Destination/data-source overlap must start at the source group’s lowest register and forces ma/ta. With vm=0, v0 cannot also supply SEW data.
- Require RV32/RV64 V 1.0, enabled VS, valid vtype and supported SEW. Body is vstart≤i<vl; prestart is unchanged. Inactive follows vma; mask tails are always agnostic. vl=0 updates no destination bits, including tails.
Pitfalls / Common Confusions
simm5 ranges from -16 to 15 and is sign-extended to SEW before comparing SEW bit patterns for inequality.
vd may be v0. Destination/data-source overlap must start at the source group’s lowest register and forces ma/ta. With vm=0, v0 cannot also supply SEW data.
Require RV32/RV64 V 1.0, enabled VS, valid vtype and supported SEW. Body is vstart≤i<vl; prestart is unchanged. Inactive follows vma; mask tails are always agnostic. vl=0 updates no destination bits, including tails.
FAQ
May destination and source overlap?
vd may be v0. Destination/data-source overlap must start at the source group’s lowest register and forces ma/ta. With vm=0, v0 cannot also supply SEW data.