Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VMERGE.VVM
RISC-V VMERGE.VVM Instruction Details
Instruction ManualOPIVVSelect element-wise between vs2 and vs1 using v0 selection mask bits, writing vd.
Instruction Syntax
vmerge.vvm vd, vs2, vs1, v0
Operand Breakdown
vd: destination vector register group.
vs2 and the second source: the two candidate inputs.
v0 selection mask: fixed selection mask; a v0 bit of 0 selects vs2, and a bit of 1 selects the second source. It is not ordinary v0.t masked execution.
VVector Data MovementMerge/Select
Instruction Behavior
VMERGE.VVM is a RISC-V V vector integer merge instruction. For each body element, v0.mask[i]=0 selects vs2[i], and v0.mask[i]=1 selects vs1[i]; here v0 is selection data, not the ordinary v0.t execution mask.
VMERGE.VVM Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VMERGE uses v0 as selection data: bit 0 selects vs2, bit 1 selects the second source, and every body element is written.
Instruction input
vmerge.vvm
v0
v0
selection-mask data, vm=0OP-V encodingvmerge.vvm
funct6
010111
vm
0
vs2
01000
vs1
01100
funct3
000
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x0020
0x0027
0x002e
0x0035
0x003c
0x0043
0x004a
0x0051
select
select
select
select
select
select
select
select
v12
0x0080
0x008b
0x0096
0x00a1
0x00ac
0x00b7
0x00c2
0x00cd
v0
1
0
1
1
1
0
1
1
v4
...
...
...
...
...
...
...
...
Current step
Show OP-V 32-bit encoding fields
vmerge.vvm uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer v0-selected merge, v0 selection data, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VMERGE.VVM treats v0 as selection-mask data: 0 selects vs2 and 1 selects vs1 vector source. It writes selected results for body elements within the current vl; it is not ordinary masked execution.
This page follows the official RISC-V V extension: vector instructions operate on body elements within the current vl. SEW, LMUL, tail policy, and mask policy come from the current vtype, usually set by vsetvli, vsetivli, or vsetvl.
VMERGE fixes v0 as selection-mask data; a v0 bit is not an ordinary execution-mask off bit.
A v0 bit of 0 selects vs2, and a v0 bit of 1 selects vs1 vector source.
VMERGE shares related OP-V encoding space with unmasked VMV forms, so vm and the vs2=v0 condition must be distinguished when reading encodings and disassembly.
Vector Execution Context
When reading VMERGE.VVM, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Mask Widening
Understand this scenario with real code like «vmerge.vvm v1, v2, v3, v0 # v0[i]? v3[i] : v2[i]».
Conditional Assignment
Understand this scenario with real code like «vmerge.vvm v1, v2, v3, v0 # v0[i]? v3[i] : v2[i]».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is OPIVV.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
v0 is selection data, not the ordinary v0.t execution mask.
A v0 bit of 0 selects vs2, and a bit of 1 selects the second source.
VMERGE and VMV share related encoding space, but their semantics are selected merge versus unmasked move.
FAQ
Which source does v0 bit 1 select in VMERGE.VVM?
v0.mask[i]=1 selects vs1 vector source; v0.mask[i]=0 selects vs2[i].
Is VMERGE an ordinary masked instruction?
No. VMERGE uses v0 as a selection input and takes each body element from one of two sources; ordinary masked instructions use v0.t to decide whether an element participates.