How does VMERGE.VVM handle masking?
It has no ordinary v0 execution mask; if a mask operand appears in the syntax, that operand is data, not an extra execution mask.
VMERGE.VVM
RISC-V VMERGE.VVM Instruction Details
Instruction ManualR-typeUse v0 mask bits to select element-wise between vs2 and the vector source, writing vd.
Instruction Syntax
vmerge.vvm vd, vs2, vs1, v0.t
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
VVector Data MovementMerge/Select
Instruction Behavior
VMERGE.VVM is a RISC-V V vector merge instruction. It explicitly uses v0.t: v0.mask[i]=0 selects vs2[i], and v0.mask[i]=1 selects the second source (vector). This is not the ordinary vm execution-mask form.
Quick Understanding & Search Notes
VMERGE uses v0.t as selection data: 0 selects vs2, 1 selects the second source. Do not treat it as the ordinary vm=0 execution mask.
v0 is the merge selection mask and is written explicitly as v0.t in the syntax.
Move instructions preserve or extend source bit patterns according to the source type.
Use vmerge forms for masked selection rather than adding an ordinary execution mask to vmv.
Common Usage Scenarios
Mask Widening
Understand this scenario with real code like «vmerge.vvm v8, v4, v6, v0.t».
Conditional Assignment
Understand this scenario with real code like «vmerge.vvm v8, v4, v6, v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
vmerge uses v0 as selection data; all body elements are updated rather than masked off
Mask source always v0
vm=1+vs2=v0 encodes as vmv.v form—different semantics