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VMV.V.V

RISC-V VMV.V.V Instruction Details

Instruction ManualOPIVV

Copies same-lane vs1 elements to vd body elements as an unmasked vector move.

Instruction Syntax

vmv.v.v vd, vs1

Operand Breakdown

vd: destination vector register group.

Source operand: from a vector register or integer register depending on the form.

VMV is an unmasked move/broadcast form; use VMERGE for selection under v0.

VVector Data MovementScalar-Vector Transfer

Related Search Terms

vmv.v.v instruction RISC-V vmv.v.v vmv.v.v encoding vmv.v.v vector copy vmv vs1 copy RVV vector copy

Instruction Behavior

VMV.V.V is an unmasked vector integer move form in the RISC-V V extension. It copies same-lane vs1 elements to vd body elements; the encoding fixes vm=1 and vs2=v0, and the syntax has no v0.t execution mask.

VMV.V.V Decode And Execute Animation

Starts from OP-V encoding fields, then shows how the unmasked VMV.V move form writes the current source value into vd body elements.

Instruction input

vmv.v.v

vdUse v0-v31

vs2

fixed encoding field, not a syntax operand

vs1Use v0-v31

unmasked move form

VLSEWvs1 elementscomma-separated

OP-V encodingvmv.v.v

funct6

010111

vs2

00000

vs1

01100

funct3

000

00100

opcode

1010111

lane

copy

v12

0x0080

0x008b

0x0096

0x00a1

0x00ac

0x00b7

0x00c2

0x00cd

active

...

Current step

Show OP-V 32-bit encoding fields

vmv.v.v uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.

This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer same-lane copy, fixed unmasked move, and vd writeback. It does not model pipelines, caches, or timing.

Quick Understanding & Search Notes

VMV.V.V is an unmasked VMV.V vector copy form that copies same-lane body elements from vs1 to vd. It performs no arithmetic and no memory access.

This page follows the official RISC-V V extension: vector instructions operate on body elements within the current vl. SEW, LMUL, tail policy, and mask policy come from the current vtype, usually set by vsetvli, vsetivli, or vsetvl.

VMV.V is an unmasked move form with encoding vm=1 and vs2=v0.

The source operand is same-lane vs1 elements; the result is copied to vd body elements within the current vl.

VMV.V performs no arithmetic, reads no memory, and does not use v0.t to select a subset of body elements.

RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations, Vector Integer Merge Instructions and Vector Integer Move Instructions

Vector Execution Context

When reading VMV.V.V, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Vector Init

Understand this scenario with real code like «vmv.v.v v1, v2 # copy body elements from v2 to v1».

Reduction Result

Understand this scenario with real code like «vmv.v.v v1, v2 # copy body elements from v2 to v1».

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is OPIVV.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

VMV.V is an unmasked move form, and the syntax has no v0.t.

The encoding fixes vs2=v0 and vm=1; do not interpret it as conditional execution under v0.

Tail elements still follow the current tail policy.

FAQ

Can VMV.V.V take v0.t?

No. VMV.V is an unmasked move form; use VMERGE when conditional selection under v0 is required.

Does VMV.V.V access memory or perform arithmetic?

No. It only copies bit patterns through registers and current body elements.