What is the destination width of VFWSUB.VV?
It writes 2*SEW floating-point results, so destination register-group use is based on the widened result.
VFWSUB.VV
RISC-V VFWSUB.VV Instruction Details
Instruction ManualOPFVVSubtract narrow vector vs1 from narrow vector vs2 and write the 2*SEW result to vd.
Instruction Syntax
vfwsub.vv vd, vs2, vs1, vm
Operand Breakdown
32-bit OP-V: opcode=1010111, funct3=001, funct6=110010. vs2 is a SEW FP source; vs1 is an SEW FP vector source.
Widen narrow sources exactly, compute vs2[i]−vs1[i], then round to 2×SEW using dynamic frm. Destination EEW=2×SEW, EMUL=2×LMUL; EMUL=2/4/8 groups align to their size; EMUL>8 is reserved.
Equal-width destination/source overlap is legal. A narrow source with EMUL≥1 may overlap only the wide destination high end; legal different-EEW overlap forces agnostic policy. One register cannot be read with two source EEWs, including an EEW=1 mask. Equal narrow source registers read equal initial values.
Omit v0.t for vm=1; include it for vm=0. Prestart stays unchanged; inactive/tail elements follow vma/vta. Undisturbed preserves old values; agnostic may preserve them or write all ones. vl=0 or vstart≥vl updates no destination elements, including tails; successful execution resets vstart=0.
V 1.0 supports RV32/RV64 and depends on F/D. Require supported source/result formats, valid vtype, and enabled VS/FS. Invalid frm use is reserved even at vl=0; vxrm is not used. Active exceptions accrue in fflags, inactive elements raise none, and NaN rules match scalar FP. This finite RNE model shows SEW=32 to binary64 only; NaNs, infinities, and full fflags are outside it.
VVector OperationsFloating-Point
Instruction Behavior
VFWSUB.VV is a RISC-V V widening floating-point subtract instruction. Both inputs are widened to 2*SEW before subtraction. The result is written to 2*SEW vd elements, with floating-point rounding, exception flags, and NaN handling following RVV FP rules.
VFWSUB.VV Decode And Execute Animation
Decode the OP-V encoding and execute lane-wise widening FP subtraction: SEW=32 sources are widened before writing 2*SEW=64 results.
Instruction input
vfwsub.vv
Execution context
LMULfixed register-group multiplier
VLENfixed vector-register length (bits)
VLMAXmaximum element count at m1
vstartprestart elements are outside this animation
frmfinite teaching context fixed at RNE; the architectural instruction uses dynamic frm
FP stateFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled
dest EEWdestination element width
vta/vmatail/inactive policy
opcodeOP-V major opcode
Encoding fields
0xc8861257
31..26
25
24..20
19..15
14..12
11..7
6..0
110010
funct6
0
vm
01000
vs2
01100
vs1
001
funct3
00100
vd
1010111
OP-V
Execution data path
lane 0: 1 - 0.5 -> 0.5
This lane follows the current-step highlight; the remaining lane results appear below.
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
1 - 0.5
0.5
i=1active
1.5 - 1
0.5
i=2skip
v0.t=0, not executed
--
i=3active
2.5 - 2
0.5
i=4active
-3 - 2.5
-5.5
i=5active
3.5 - 3
0.5
i=6skip
v0.t=0, not executed
--
i=7active
4.5 - 4
0.5
This finite subtraction model fixes SEW=32, LMUL=m1, VLEN=4096, vstart=0, valid vtype, enabled VS/FS, frm=RNE, and ta/ma. vs2 is represented as binary32 and widened exactly; the right source is represented as binary32 and widened exactly before vs2 minus right source rounds to binary64. Destination and wide vs2 use even two-register groups; narrow sources may overlap only the destination high end, and equal narrow sources require equal initial values. VL=0 updates no destination elements, including tails; inactive/tail values have no definite display. NaNs, infinities, overflow, full fflags, and microarchitectural cycles are outside this model; the real instruction uses dynamic frm, with invalid frm use reserved even at VL=0.
Quick Understanding & Search Notes
VFWSUB.VV subtracts vs1 from vs2; it is not a reversed subtract.
For .VV/.VF forms, narrow inputs are widened first, and vd elements are 2*SEW wide.
Active subtraction rounds using dynamic frm; invalid frm use is reserved, including at vl=0. vxrm is not used; only active-element FP exceptions accrue in fflags.
Vector FP32/FP64 operations require the corresponding scalar F/D support; half precision is controlled by the relevant vector half-precision extension.
vm=0 uses v0.t; omitting the mask gives vm=1. Prestart stays unchanged; inactive/tail elements follow vma/vta without guaranteed zeros. At vl=0 or vstart≥vl, no destination elements, including tails, update.
Vector Execution Context
32-bit OP-V: opcode=1010111, funct3=001, funct6=110010. vs2 is a SEW FP source; vs1 is an SEW FP vector source.
Widen narrow sources exactly, compute vs2[i]−vs1[i], then round to 2×SEW using dynamic frm. Destination EEW=2×SEW, EMUL=2×LMUL; EMUL=2/4/8 groups align to their size; EMUL>8 is reserved.
Equal-width destination/source overlap is legal. A narrow source with EMUL≥1 may overlap only the wide destination high end; legal different-EEW overlap forces agnostic policy. One register cannot be read with two source EEWs, including an EEW=1 mask. Equal narrow source registers read equal initial values.
Omit v0.t for vm=1; include it for vm=0. Prestart stays unchanged; inactive/tail elements follow vma/vta. Undisturbed preserves old values; agnostic may preserve them or write all ones. vl=0 or vstart≥vl updates no destination elements, including tails; successful execution resets vstart=0.
V 1.0 supports RV32/RV64 and depends on F/D. Require supported source/result formats, valid vtype, and enabled VS/FS. Invalid frm use is reserved even at vl=0; vxrm is not used. Active exceptions accrue in fflags, inactive elements raise none, and NaN rules match scalar FP. This finite RNE model shows SEW=32 to binary64 only; NaNs, infinities, and full fflags are outside it.
Common Usage Scenarios
High-Precision Difference
Assume valid e32,m1, enabled VS/FS, supported formats, VLMAX≥4, and a0=4; vsetvli sets vl=4 and vstart=0. frm=RNE; Omit v0.t for unmasked execution. v4(binary32)=[2,4,-2,0], v6(binary32)=[3,-1,2,5] → v2/v3(binary64)=[-1,5,-4,-5]. Inactive/tail elements follow ma/ta without guaranteed zeros.
Pre-Use Checklist
Syntax Check
- 32-bit OP-V: opcode=1010111, funct3=001, funct6=110010. vs2 is a SEW FP source; vs1 is an SEW FP vector source.
- Widen narrow sources exactly, compute vs2[i]−vs1[i], then round to 2×SEW using dynamic frm. Destination EEW=2×SEW, EMUL=2×LMUL; EMUL=2/4/8 groups align to their size; EMUL>8 is reserved.
Semantic Check
- Equal-width destination/source overlap is legal. A narrow source with EMUL≥1 may overlap only the wide destination high end; legal different-EEW overlap forces agnostic policy. One register cannot be read with two source EEWs, including an EEW=1 mask. Equal narrow source registers read equal initial values.
- Omit v0.t for vm=1; include it for vm=0. Prestart stays unchanged; inactive/tail elements follow vma/vta. Undisturbed preserves old values; agnostic may preserve them or write all ones. vl=0 or vstart≥vl updates no destination elements, including tails; successful execution resets vstart=0.
- V 1.0 supports RV32/RV64 and depends on F/D. Require supported source/result formats, valid vtype, and enabled VS/FS. Invalid frm use is reserved even at vl=0; vxrm is not used. Active exceptions accrue in fflags, inactive elements raise none, and NaN rules match scalar FP. This finite RNE model shows SEW=32 to binary64 only; NaNs, infinities, and full fflags are outside it.
Pitfalls / Common Confusions
Destination EEW=2×SEW and EMUL=2×LMUL; EMUL=2/4/8 groups align to their size, and EMUL>8 is reserved. A masked destination cannot include v0; narrow-source overlap is allowed only at the destination high end under the specified conditions.
Vector FP32/FP64 operations require matching scalar F/D support; FP16 operation is not implied by V alone.
FAQ
How does VFWSUB.VV handle masking?
With vm=0, v0 selects active elements; with vm=1, all body elements participate. Inactive and tail elements follow the current policies.