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VFWSUB.WV

RISC-V VFWSUB.WV Instruction Details

Instruction ManualR-type

Subtract narrow vector vs1 from wide vector vs2 and write the 2*SEW result to vd.

Instruction Syntax

vfwsub.wv vd, vs2, vs1, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VZvfhVector OperationsFloating-Point
Related Search Terms
VFWSUB.WV instructionRISC-V VFWSUB.WVvfwsub.wv syntaxvfwsub.wv RVVwidening FP subtractRVV floating point

Instruction Behavior

VFWSUB.WV is a RISC-V V widening floating-point subtract instruction. The left operand vs2 is already 2*SEW wide, and the right operand is widened as needed before subtraction. The result is written to 2*SEW vd elements, with floating-point rounding, exception flags, and NaN handling following RVV FP rules.

Quick Understanding & Search Notes

VFWSUB.WV subtracts vs1 from vs2; it is not a reversed subtract.

For .WV/.WF forms, vs2 is the wide input, and vd elements are 2*SEW wide.
Floating-point operations use frm or instruction-defined FP rounding rules; vxrm is only for fixed-point rounding instructions.
Vector FP32/FP64 operations require the corresponding scalar F/D support; half precision is controlled by the relevant vector half-precision extension.
vm=0 uses v0 as the execution mask and vm=1 is unmasked; inactive and tail elements follow the current vma/vta policy.
RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations

Vector Execution Context

When reading VFWSUB.WV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

High-Precision Difference

e.g., sub t0, a0, a1 — compute the difference a0 - a1.

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Dest EMUL=2*LMUL needs double registers. Masking via v0. Mind operand order vs2-(scalar/vector).
Vector FP32/FP64 operations require matching scalar F/D support; FP16 operation is not implied by V alone.

FAQ

What is the destination width of VFWSUB.WV?

It writes 2*SEW floating-point results, so destination register-group use is based on the widened result.

How does VFWSUB.WV handle masking?

With vm=0, v0 selects active elements; with vm=1, all body elements participate. Inactive and tail elements follow the current policies.