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VFWADD.VF

RISC-V VFWADD.VF Instruction Details

Instruction ManualOPFVF

Add SEW float elements of vs2 with f[rs1], writing widened result (2×SEW) to vd.

Instruction Syntax

vfwadd.vf vd, vs2, rs1, vm

Operand Breakdown

vd: destination vector register group.

vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.

vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.

VVector OperationsFloating-Point

Related Search Terms

VFWADD.VF instruction RISC-V VFWADD.VF vfwadd.vf syntax vfwadd.vf RVV widening add vfwadd.vf floating-point widening

Instruction Behavior

VFWADD.VF performs widening floating-point addition. SEW-wide source elements are added and the result is written to a 2*SEW-wide vd. Vector FP32/FP64 operation requires the corresponding scalar F/D support; FP16 is controlled by the relevant vector half-precision extensions; do not assume the base V extension includes half-precision arithmetic.

VFWADD.VF Decode And Execute Animation

Decode the OP-V encoding and execute lane-wise widening FP addition: SEW=32 sources are widened before writing 2*SEW=64 results.

Instruction input

vfwadd.vf

vdUse v0-v31vs2Use v0-v31rs1FP register f0-f31/ABIvmexecution mask control

Execution context

VLSEW

LMULm1fixed register-group multiplier

VLEN4096fixed vector-register length (bits)

VLMAX128maximum element count at m1

vstart0prestart elements are outside this animation

frmRNEfinite teaching context fixed at RNE; the architectural instruction uses dynamic frm

FP stateFS enabledFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled

dest EEW64destination element width

vta/vmata, matail/inactive policy

opcode1010111OP-V major opcode

vs2 elementsComma-separated finite values, count must equal VL, representable as finite binary32f[rs1]finite FP demo value, representable as finite binary32v0 mask bits0/1 string, length must equal VL

Encoding fields

0xc0855257

31..26

24..20

19..15

14..12

11..7

6..0

110000

funct6

01000

vs2

01010

rs1

101

funct3

00100

1010111

OP-V

Execution data path

lane 0: 1 + 1.5 -> 2.5

This lane follows the current-step highlight; the remaining lane results appear below.

Step 1 / 15

Read OP-V encoding fields

V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.

Lane results

Long vectors scroll inside this module without page overflow.

i=0active

1 + 1.5

2.5

i=1active

1.5 + 1.5

i=2skip

v0.t=0, not executed

i=3active

2.5 + 1.5

i=4active

-3 + 1.5

-1.5

i=5active

3.5 + 1.5

i=6skip

v0.t=0, not executed

i=7active

4.5 + 1.5

In the fixed VLEN=4096, LMUL=m1, vstart=0 teaching context, source elements are represented as SEW=32 / binary32, widened exactly to binary64, then addition executes in binary64 before writing the 2*SEW=64 result. This animation uses RNE as a checkable demo mode; NaNs, infinities, and exception flags remain governed by the official RVV FP rules.

Quick Understanding & Search Notes

VFWADD.VF keeps the add result at wider precision, unlike single-width VFADD.

Widening forms change destination element width and register-group usage, so LMUL/EMUL must be checked.

The operation applies only to active elements from vstart through vl-1; this animation fixes vstart=0, while real vstart>=vl updates no body elements. Inactive and tail elements follow vma/vta.

Except for dedicated mask forms, vm=0 uses v0 as the execution mask and vm=1 is unmasked.

Floating-point operations follow the vector FP rules: normal FP operations use frm rounding and set FP exception flags; fixed-point vxrm does not control them.

RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations

Vector Execution Context

When reading VFWADD.VF, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vf: one vector source and one floating-point scalar source participate.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

High-Precision Accum

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfwadd.vf v2, v4, ft0 # 32b→64b result in v2-v3».

Mixed Precision

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfwadd.vf v2, v4, ft0 # 32b→64b result in v2-v3».

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is OPFVF.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Dest EMUL=2×LMUL — needs double register group for widened result.

Widening changes the result element width from SEW to 2*SEW (for example, 32-bit to 64-bit); it does not mean significand precision doubles. This page's FP32-to-FP64 demonstration widens source values exactly before addition.

Vector FP32/FP64 operations require matching scalar F/D support; FP16 operation is not implied by V alone.

FAQ

Do these floating-point instructions use vxrm?

No. Ordinary RVV floating-point operations and FP conversions use floating-point frm or an instruction-specified fixed rounding mode; vxrm is for fixed-point rounding instructions.