Do these floating-point instructions use vxrm?
No. Ordinary RVV floating-point operations and FP conversions use floating-point frm or an instruction-specified fixed rounding mode; vxrm is for fixed-point rounding instructions.
VFWADD.VF
RISC-V VFWADD.VF Instruction Details
Instruction ManualR-typeAdd SEW float elements of vs2 with f[rs1], writing widened result (2×SEW) to vd.
Instruction Syntax
vfwadd.vf vd, vs2, rs1, vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
VZvfhVector OperationsFloating-Point
Instruction Behavior
VFWADD.VF performs widening floating-point addition. SEW-wide source elements are added and the result is written to a 2*SEW-wide vd. Vector FP32/FP64 operation requires the corresponding scalar F/D support; FP16 is controlled by the relevant vector half-precision extensions; do not assume the base V extension includes half-precision arithmetic.
Quick Understanding & Search Notes
VFWADD.VF keeps the add result at wider precision, unlike single-width VFADD.
Widening forms change destination element width and register-group usage, so LMUL/EMUL must be checked.
The operation applies only to active elements within vl; inactive and tail elements follow the current vma/vta policy.
Except for dedicated mask forms, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
Floating-point operations follow the vector FP rules: normal FP operations use frm rounding and set FP exception flags; fixed-point vxrm does not control them.
Common Usage Scenarios
High-Precision Accum
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfwadd.vf v2, v4, ft0 # 32b→64b result in v2-v3».
Mixed Precision
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfwadd.vf v2, v4, ft0 # 32b→64b result in v2-v3».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Dest EMUL=2×LMUL — needs double register group for widened result.
Widening doubles precision (e.g., 32-bit → 64-bit).
Vector FP32/FP64 operations require matching scalar F/D support; FP16 operation is not implied by V alone.