RISC-V VFWADD.WF Instruction Details

Instruction ManualR-type

Add 2*SEW float elements of vs2 with widened f[rs1], writing 2*SEW result to vd.

Instruction Syntax

vfwadd.wf vd, vs2, rs1, vm

Operand Breakdown

Destination rd: register receiving the operation result.

Source rs1: register holding the first operand.

Source rs2: register holding the second operand.

VZvfhVector OperationsFloating-Point

Related Search Terms

VFWADD.WF instruction RISC-V VFWADD.WF vfwadd.wf syntax vfwadd.wf RVV widening add 2*SEW

Instruction Behavior

VFWADD.WF performs widening floating-point addition. One source operand is already 2*SEW wide and the other is widened before addition. Vector FP32/FP64 operation requires the corresponding scalar F/D support; FP16 is controlled by the relevant vector half-precision extensions; do not assume the base V extension includes half-precision arithmetic.

Quick Understanding & Search Notes

VFWADD.WF keeps the add result at wider precision, unlike single-width VFADD.

Widening forms change destination element width and register-group usage, so LMUL/EMUL must be checked.

The operation applies only to active elements within vl; inactive and tail elements follow the current vma/vta policy.

Except for dedicated mask forms, vm=0 uses v0 as the execution mask and vm=1 is unmasked.

Floating-point operations follow the vector FP rules: normal FP operations use frm rounding and set FP exception flags; fixed-point vxrm does not control them.

RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations

Common Usage Scenarios

High-Precision Accum

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfwadd.wf v2, v4, ft0 # wide(64b)+widened(ft0)».

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is R-type.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

.wf: w=wide src (EEW=2*SEW), f=scalar. vd and vs2 same width (both 2*SEW).

Vector FP32/FP64 operations require matching scalar F/D support; FP16 operation is not implied by V alone.

FAQ

Do these floating-point instructions use vxrm?

No. Ordinary RVV floating-point operations and FP conversions use floating-point frm or an instruction-specified fixed rounding mode; vxrm is for fixed-point rounding instructions.