Do these floating-point instructions use vxrm?
No. Ordinary RVV floating-point operations and FP conversions use floating-point frm or an instruction-specified fixed rounding mode; vxrm is for fixed-point rounding instructions.
VFWADD.WV
RISC-V VFWADD.WV Instruction Details
Instruction ManualOPFVVAdd 2*SEW float elements of vs2 with widened vs1 (SEW) elements, writing 2*SEW result to vd.
Instruction Syntax
vfwadd.wv vd, vs2, vs1, vm
Operand Breakdown
Syntax: vfwadd.wv vd, vs2, vs1[, v0.t]. 32-bit OP-V: opcode=1010111, funct3=001, funct6=110100. vs1 selects the narrow vector source.
vs2 and vd have EEW=2×SEW, EMUL=2×LMUL; vs1 has EEW=SEW, EMUL=LMUL. Groups with EMUL=2/4/8 align to their size; EMUL>8 is reserved, while EMUL≤1 does not require even register numbers.
Narrow vs1 widens exactly before addition to wide vs2 under dynamic frm. Wide vs2 may overlap the equal-width destination, but cannot share a register with narrow vs1. Every vector FP instruction still requires valid frm, including at vl=0; invalid frm use is reserved. vxrm is not used.
Narrow-source/wide-destination overlap requires source EMUL≥1 and equal highest register numbers; legal different-EEW overlap forces mask/tail agnostic. A masked destination cannot include v0; one register cannot be read as different-EEW data and mask sources.
Optional v0.t means vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled; only active-element exceptions accrue in fflags. Prestart elements do not update or raise exceptions. At vl=0 or vstart≥vl no destination elements, including tails, update. Other inactive/tail elements follow vma/vta; ta/ma does not guarantee zeros. Successful execution resets vstart=0.
Require the extensions, supported FP formats, valid vtype, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. This animation fixes SEW=32, LMUL=m1, VLEN=4096, vstart=0, ta/ma, and finite inputs; it does not fully simulate NaNs, infinities, fflags, or microarchitectural cycles.
VVector OperationsFloating-Point
Instruction Behavior
VFWADD.WV computes vd[i] = vs2[i] + widen(vs1[i]) for active elements. vs2 is already 2×SEW wide, vs1 is SEW wide, and the result is 2×SEW wide. The narrow FP source widens exactly before double-width addition under dynamic frm. The animation shows finite binary64 plus binary32 values under RNE.
VFWADD.WV Decode And Execute Animation
Decode the OP-V encoding and execute lane-wise widening FP addition: vs2 is already 2*SEW=64 wide, while vs1[i] is exactly widened from SEW=32 before writing the 2*SEW=64 result.
Instruction input
vfwadd.wv
Execution context
LMULfixed register-group multiplier
VLENfixed vector-register length (bits)
VLMAXmaximum element count at m1
vstartprestart elements are outside this animation
frmfinite teaching context fixed at RNE; the architectural instruction uses dynamic frm
FP stateFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled
dest EEWdestination element width
vs2 EEWwide left operand element width
vta/vmatail/inactive policy
opcodeOP-V major opcode
Encoding fields
0xd0861257
31..26
25
24..20
19..15
14..12
11..7
6..0
110100
funct6
0
vm
01000
vs2
01100
vs1
001
funct3
00100
vd
1010111
OP-V
Execution data path
lane 0: 1 + 0.5 -> 1.5
This lane follows the current-step highlight; the remaining lane results appear below.
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
1 + 0.5
1.5
i=1active
1.5 + 1
2.5
i=2skip
v0.t=0, not executed
--
i=3active
2.5 + 2
4.5
i=4active
-3 + 2.5
-0.5
i=5active
3.5 + 3
6.5
i=6skip
v0.t=0, not executed
--
i=7active
4.5 + 4
8.5
This teaching model fixes SEW=32, LMUL=m1, VLEN=4096, vstart=0, valid vtype, enabled VS/FS, and ta/ma. vs2 is binary64, vs1 is binary32, and the sum rounds to binary64 under RNE. Inactive/tail elements have no definite displayed values; VL=0 updates no destination elements. NaNs, infinities, fflags, and microarchitectural cycles are outside this model.
Quick Understanding & Search Notes
VFWADD.WV keeps the add result at wider precision, unlike single-width VFADD.
32-bit OP-V: opcode=1010111, funct3=001, funct6=110100; vs1 selects the narrow vector source.
vs2 and vd have EEW=2×SEW, EMUL=2×LMUL; vs1 has EEW=SEW, EMUL=LMUL. Groups with EMUL=2/4/8 align to their size; EMUL>8 encodings are reserved, while EMUL≤1 does not require even register numbers. Narrow-source overlap requires source EMUL≥1 and equal highest source/destination register numbers; legal different-EEW overlap forces mask/tail agnostic.
Wide vs2 may overlap the equal-width destination; wide vs2 and narrow vs1 cannot share a source register, which would read one register at different EEWs.
Dynamic frm controls double-width addition rounding; active-element exceptions accrue in fflags. Every vector FP instruction requires valid frm, even without rounding or at vl=0; invalid frm use is reserved. vxrm does not control these operations.
vm denotes optional v0.t; omission means vm=1, while v0.t means vm=0. Active elements satisfy vstart≤i<vl with the mask enabled. A masked destination cannot overlap v0; one register cannot be read as both data and an EEW=1 mask source.
Prestart elements do not update or raise exceptions. At vl=0 or vstart≥vl, no destination elements, including tails, are updated. Other inactive/tail elements follow vma/vta; ta/ma permits retaining old values or writing all ones, without guaranteed zeros. Successful execution resets vstart=0.
Require the extensions, supported FP widths, valid vtype, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. This animation fixes SEW=32, LMUL=m1, VLEN=4096, vstart=0, and ta/ma to demonstrate 64-bit results; NaNs, infinities, and fflags are not fully simulated.
Vector Execution Context
Syntax: vfwadd.wv vd, vs2, vs1[, v0.t]. 32-bit OP-V: opcode=1010111, funct3=001, funct6=110100. vs1 selects the narrow vector source.
vs2 and vd have EEW=2×SEW, EMUL=2×LMUL; vs1 has EEW=SEW, EMUL=LMUL. Groups with EMUL=2/4/8 align to their size; EMUL>8 is reserved, while EMUL≤1 does not require even register numbers.
Narrow vs1 widens exactly before addition to wide vs2 under dynamic frm. Wide vs2 may overlap the equal-width destination, but cannot share a register with narrow vs1. Every vector FP instruction still requires valid frm, including at vl=0; invalid frm use is reserved. vxrm is not used.
Narrow-source/wide-destination overlap requires source EMUL≥1 and equal highest register numbers; legal different-EEW overlap forces mask/tail agnostic. A masked destination cannot include v0; one register cannot be read as different-EEW data and mask sources.
Optional v0.t means vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled; only active-element exceptions accrue in fflags. Prestart elements do not update or raise exceptions. At vl=0 or vstart≥vl no destination elements, including tails, update. Other inactive/tail elements follow vma/vta; ta/ma does not guarantee zeros. Successful execution resets vstart=0.
Require the extensions, supported FP formats, valid vtype, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. This animation fixes SEW=32, LMUL=m1, VLEN=4096, vstart=0, ta/ma, and finite inputs; it does not fully simulate NaNs, infinities, fflags, or microarchitectural cycles.
Common Usage Scenarios
Add a narrow FP vector to a wide FP vector
Assume enabled extensions and VS/FS, valid vtype, supported formats, frm=RNE, e32,m1, VLMAX≥4, and a0=4; vsetvli sets vl=4 and vstart=0. Omit v0.t for unmasked execution: v4/v5(binary64)=[1,2,-3,0], v8(binary32)=[0.5,0.5,0.5,0.5] → v2/v3=[1.5,2.5,-2.5,0.5]. Tails follow ta without guaranteed zeros.
Mixed-precision addition
Assume enabled extensions and VS/FS, valid vtype, supported formats, frm=RNE, e32,m1, VLMAX≥4, and a0=4; vsetvli sets vl=4 and vstart=0. Omit v0.t for unmasked execution: v4/v5(binary64)=[1,2,-3,0], v8(binary32)=[0.5,0.5,0.5,0.5] → v2/v3=[1.5,2.5,-2.5,0.5]. Tails follow ta without guaranteed zeros.
Pre-Use Checklist
Syntax Check
- Syntax: vfwadd.wv vd, vs2, vs1[, v0.t]. 32-bit OP-V: opcode=1010111, funct3=001, funct6=110100. vs1 selects the narrow vector source.
- vs2 and vd have EEW=2×SEW, EMUL=2×LMUL; vs1 has EEW=SEW, EMUL=LMUL. Groups with EMUL=2/4/8 align to their size; EMUL>8 is reserved, while EMUL≤1 does not require even register numbers.
Semantic Check
- Narrow vs1 widens exactly before addition to wide vs2 under dynamic frm. Wide vs2 may overlap the equal-width destination, but cannot share a register with narrow vs1. Every vector FP instruction still requires valid frm, including at vl=0; invalid frm use is reserved. vxrm is not used.
- Narrow-source/wide-destination overlap requires source EMUL≥1 and equal highest register numbers; legal different-EEW overlap forces mask/tail agnostic. A masked destination cannot include v0; one register cannot be read as different-EEW data and mask sources.
- Optional v0.t means vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled; only active-element exceptions accrue in fflags. Prestart elements do not update or raise exceptions. At vl=0 or vstart≥vl no destination elements, including tails, update. Other inactive/tail elements follow vma/vta; ta/ma does not guarantee zeros. Successful execution resets vstart=0.
- Require the extensions, supported FP formats, valid vtype, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. This animation fixes SEW=32, LMUL=m1, VLEN=4096, vstart=0, ta/ma, and finite inputs; it does not fully simulate NaNs, infinities, fflags, or microarchitectural cycles.
Pitfalls / Common Confusions
vs2 and vd have EEW=2×SEW, EMUL=2×LMUL; vs1 has EEW=SEW, EMUL=LMUL. Groups with EMUL=2/4/8 align to their size; EMUL>8 encodings are reserved, while EMUL≤1 does not require even register numbers. Narrow-source overlap requires source EMUL≥1 and equal highest source/destination register numbers; legal different-EEW overlap forces mask/tail agnostic.
Dynamic frm controls double-width addition rounding; active-element exceptions accrue in fflags.
The animation's limits are narrower than the architectural legal input domain; represent decimal FP inputs as binary32/binary64 before performing the operation.