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VFWSUB.VF

RISC-V VFWSUB.VF Instruction Details

Instruction ManualOPFVF

Subtract floating-point scalar f[rs1] from narrow vector vs2 and write the 2*SEW result to vd.

Instruction Syntax

vfwsub.vf vd, vs2, rs1, vm

Operand Breakdown

vd: destination vector register group.

vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.

vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.

VVector OperationsFloating-Point

Related Search Terms

VFWSUB.VF instruction RISC-V VFWSUB.VF vfwsub.vf syntax vfwsub.vf RVV widening FP subtract RVV floating point

Instruction Behavior

VFWSUB.VF is a RISC-V V widening floating-point subtract instruction. Both inputs are widened to 2*SEW before subtraction. The result is written to 2*SEW vd elements, with floating-point rounding, exception flags, and NaN handling following RVV FP rules.

VFWSUB.VF Decode And Execute Animation

Decode the OP-V encoding and execute lane-wise widening FP subtraction: SEW=32 sources are widened before writing 2*SEW=64 results.

Instruction input

vfwsub.vf

vdUse v0-v31vs2Use v0-v31rs1FP register f0-f31/ABIvmexecution mask control

Execution context

VLSEW

LMULm1fixed register-group multiplier

VLEN4096fixed vector-register length (bits)

VLMAX128maximum element count at m1

vstart0prestart elements are outside this animation

frmRNEfinite teaching context fixed at RNE; the architectural instruction uses dynamic frm

FP stateFS enabledFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled

dest EEW64destination element width

vta/vmata, matail/inactive policy

opcode1010111OP-V major opcode

vs2 elementsComma-separated finite values, count must equal VL, representable as finite binary32f[rs1]finite FP demo value, representable as finite binary32v0 mask bits0/1 string, length must equal VL

Encoding fields

0xc8855257

31..26

24..20

19..15

14..12

11..7

6..0

110010

funct6

01000

vs2

01010

rs1

101

funct3

00100

1010111

OP-V

Execution data path

lane 0: 1 - 1.5 -> -0.5

This lane follows the current-step highlight; the remaining lane results appear below.

Step 1 / 15

Read OP-V encoding fields

V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.

Lane results

Long vectors scroll inside this module without page overflow.

i=0active

1 - 1.5

-0.5

i=1active

1.5 - 1.5

i=2skip

v0.t=0, not executed

i=3active

2.5 - 1.5

i=4active

-3 - 1.5

-4.5

i=5active

3.5 - 1.5

i=6skip

v0.t=0, not executed

i=7active

4.5 - 1.5

In the fixed VLEN=4096, LMUL=m1, vstart=0 teaching context, source elements are represented as SEW=32 / binary32, widened exactly to binary64, then subtraction executes in binary64 before writing the 2*SEW=64 result. This animation uses RNE as a checkable demo mode; NaNs, infinities, and exception flags remain governed by the official RVV FP rules.

Quick Understanding & Search Notes

VFWSUB.VF subtracts f[rs1] from vs2; it is not a reversed subtract.

For .VV/.VF forms, narrow inputs are widened first, and vd elements are 2*SEW wide.

Floating-point operations use frm or instruction-defined FP rounding rules; vxrm is only for fixed-point rounding instructions.

Vector FP32/FP64 operations require the corresponding scalar F/D support; half precision is controlled by the relevant vector half-precision extension.

vm=0 uses v0 as the execution mask and vm=1 is unmasked; inactive and tail elements follow the current vma/vta policy.

RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations

Vector Execution Context

When reading VFWSUB.VF, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vf: one vector source and one floating-point scalar source participate.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

High-Precision Difference

e.g., sub t0, a0, a1 — compute the difference a0 - a1.

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is OPFVF.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Dest EMUL=2*LMUL needs double registers. Masking via v0. Mind operand order vs2-(scalar/vector).

Vector FP32/FP64 operations require matching scalar F/D support; FP16 operation is not implied by V alone.

FAQ

What is the destination width of VFWSUB.VF?

It writes 2*SEW floating-point results, so destination register-group use is based on the widened result.

How does VFWSUB.VF handle masking?

With vm=0, v0 selects active elements; with vm=1, all body elements participate. Inactive and tail elements follow the current policies.