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VFCVT.XU.F.V

RISC-V VFCVT.XU.F.V Instruction Details

Instruction ManualR-type

VFCVT.XU.F.V performs an RVV single-width FP-to-unsigned-integer conversion for each active element and writes the result to vd[i].

Instruction Syntax

vfcvt.xu.f.v vd, vs2, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VZvfhVector Type ConvertFloating-Point
Related Search Terms
VFCVT.XU.F.V instructionRISC-V VFCVT.XU.F.Vvfcvt.xu.f.v syntaxvfcvt.xu.f.v encodingRVV single-width convertFP to unsigned intVFCVT frm roundingvfcvt.xu.f.v v0.t

Instruction Behavior

VFCVT.XU.F.V is a RISC-V V-extension single-width floating-point/integer conversion instruction with syntax vfcvt.xu.f.v vd, vs2, vm. For active elements within vl, it reads vs2[i], performs a same-SEW FP-to-unsigned-integer conversion, and writes the result to vd[i]; vm=0 uses v0.t as the execution mask and vm=1 is unmasked. The encoding uses OP-V, funct6=010010, funct3=001, and vs1 selector 00000; it uses the dynamic frm rounding mode.

VFCVT.XU.F.V Decode And Execute Animation

Decode the OP-V encoding and execute a VFUNARY0 single-width conversion lane by lane: each active lane converts the FP value in vs2[i] to a unsigned integer.

Step 1 / 15
Read OP-V encoding fields

V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.

Instruction input
vfcvt.xu.f.v
Execution context
frm
RNE
demo dynamic rounding mode
vta/vma
ta, ma
tail/inactive policy
opcode
1010111
OP-V major opcode
vs1
00000
VFUNARY0 conversion selector
Encoding fields
0x48801257
31..26
25
24..20
19..15
14..12
11..7
6..0
010010
funct6
0
vm
01000
vs2
00000
vs1/sel
001
funct3
00100
vd
1010111
OP-V
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
round.frm_unsigned(0.25)
0
i=1active
round.frm_unsigned(1.5)
2
i=2skip
v0.t=0, not executed
--
i=3active
round.frm_unsigned(3.75)
4
i=4active
round.frm_unsigned(7.125)
7
i=5active
round.frm_unsigned(8.5)
8
i=6skip
v0.t=0, not executed
--
i=7active
round.frm_unsigned(31.25)
31
SEW=32 / binary32 demo values cover finite FP inputs whose rounded integer result fits this demo's integer range. The non-RTZ form uses dynamic rounding; this animation uses RNE as a checkable demo mode. NaN, infinity, out-of-range cases, and fflags still follow the official RVV/scalar FP conversion rules; the 64-bit integer demo range avoids JavaScript unsafe-integer edges.

Quick Understanding & Search Notes

VFCVT.XU.F.V is best understood as a VFUNARY0 single-width conversion: after decoding vs1=00000, active elements convert vs2[i] from FP to an unsigned integer.

In the OP-V encoding, funct6=010010 and funct3=001 select the vector FP/integer conversion group, and vs1=00000 selects VFCVT.XU.F.V.
The syntax input contains only vd, vs2, and vm; VL, SEW, frm, v0.t, and element values are execution context.
This is a single-width conversion, so input and output both use the current SEW.
When rounding is required, the floating-point dynamic rounding mode frm is used.
Only active elements within vl execute; vm=0 uses v0.t and vm=1 is unmasked.
NaNs, infinities, out-of-range cases, and inexact/invalid flags follow the official RVV and scalar FP conversion rules.
This page animation currently demonstrates the SEW=32/64 binary32/binary64 paths; SEW=16 half-precision behavior is governed by the official vector half-precision support rules such as Zvfh/Zvfhmin.
RISC-V Unprivileged ISA Manual: V extension vector FP/integer conversion instructionsRISC-V Unprivileged ISA Manual: scalar FP conversion and rounding rules

Vector Execution Context

When reading VFCVT.XU.F.V, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

FP results to integer vectors

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfcvt.xu.f.v v1, v2».

frm-rounded conversion

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfcvt.xu.f.v v1, v2».

Mixed-type vector math

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfcvt.xu.f.v v1, v2».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

This is a single-width conversion: input and output both use the current SEW; do not treat it as a VFWCVT widening or VFNCVT narrowing form.
When rounding is required, it uses floating-point frm; do not confuse this with the fixed-point rounding mode vxrm.
VFCVT.XU.F.V interprets source elements as FP values before converting them to unsigned integers; it is not FCLASS classification or a bit-pattern move.
With vm=0, v0.t selects active elements only; masked-off elements do not produce the conversion result shown by the animation.
NaNs, infinities, out-of-range values, and FP exception flags follow the official FP conversion rules; the page animation demonstrates only finite, checkable in-range examples.
Do not read the SEW=32/64 animation examples as a complete SEW=16 half-precision simulator; half-precision conversion still follows the official Zvfh/Zvfhmin-related rules.

FAQ

Is VFCVT.XU.F.V a widening or narrowing conversion?

No. This VFCVT.XU.F.V form is a single-width VFCVT conversion: input and output both use the current SEW. Widening uses VFWCVT, and narrowing uses VFNCVT.

Where does VFCVT.XU.F.V take its rounding mode from?

When rounding is required, it uses the floating-point dynamic rounding mode frm, not the fixed-point vxrm.

How does VFCVT.XU.F.V use the mask operand?

With vm=0, only active elements selected by v0.t are converted; vm=1 is unmasked. Inactive and tail elements follow the current vma/vta policies.