Is VFCVT.F.XU.V a widening or narrowing conversion?
No. This VFCVT.F.XU.V form is a single-width VFCVT conversion: input and output both use the current SEW. Widening uses VFWCVT, and narrowing uses VFNCVT.
VFCVT.F.XU.V
RISC-V VFCVT.F.XU.V Instruction Details
Instruction ManualOPFVVVFCVT.F.XU.V performs an RVV single-width unsigned-integer-to-FP conversion for each active element and writes the result to vd[i].
Instruction Syntax
vfcvt.f.xu.v vd, vs2, vm
Operand Breakdown
vd and vs2 are SEW-wide vector groups; same-EEW source/destination overlap is allowed. VFADD.VV also reads a SEW-wide vs1 vector, and equal source registers read equal initial values. Unary instructions use the encoded vs1 bits as a fixed selector.
Require V, enabled VS/FS and supported vtype. V supports binary32/64; these instructions at SEW=16 require Zvfh, not Zvfhmin alone. FS=Off raises illegal instruction; with H and V=1, vsstatus.FS/VS must also be enabled.
Active elements satisfy vstart≤i<vl and (vm=1 or v0[i]=1); omitting v0.t means vm=1. Prestart elements are unchanged, and inactive/tail elements follow vma/vta. VL=0 or vstart≥vl leaves the entire destination unchanged; successful completion resets vstart=0. Implementations may reject nonzero vstart values they cannot produce.
Masked vd cannot overlap v0; v0 cannot supply both an EEW=1 mask and SEW data source. Invalid frm use is reserved even without rounding, at VL=0 or vstart≥vl; an illegal-instruction exception is not guaranteed by that rule.
Dynamic frm controls rounding; only active-element FP exceptions accrue in fflags. Fixed-point vxrm is not used. Integer-to-FP conversion is numeric, not a bit move, and inexact conversion sets NX.
VVector Type ConvertFloating-Point
Instruction Behavior
VFCVT.F.XU.V is a RISC-V V-extension single-width floating-point/integer conversion instruction with syntax vfcvt.f.xu.v vd, vs2, vm. For active elements within vl, it reads vs2[i], performs a same-SEW unsigned-integer-to-FP conversion, and writes the result to vd[i]; vm=0 uses v0.t as the execution mask and vm=1 is unmasked. The encoding uses OP-V, funct6=010010, funct3=001, and vs1 selector 00010; it uses dynamic frm when rounding is required.
VFCVT.F.XU.V Decode And Execute Animation
Decode the OP-V encoding and execute a VFUNARY0 single-width conversion lane by lane: each active lane converts the unsigned integer in vs2[i] to a same-SEW FP value.
Instruction input
vfcvt.f.xu.v
Execution context
LMULfixed register-group multiplier
VLENfixed vector-register length (bits)
VLMAXmaximum element count at m1
vstartprestart elements are outside this animation
frmfinite teaching context fixed at RNE; the architectural instruction uses dynamic frm
FP stateFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled
vta/vmatail/inactive policy
opcodeOP-V major opcode
vs1VFUNARY0 conversion selector
Encoding fields
0x48811257
31..26
25
24..20
19..15
14..12
11..7
6..0
010010
funct6
0
vm
01000
vs2
00010
vs1/sel
001
funct3
00100
vd
1010111
OP-V
Execution data path
lane 0: uint_to_float(0) -> 0
This lane follows the current-step highlight; the remaining lane results appear below.
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
uint_to_float(0)
0
i=1active
uint_to_float(1)
1
i=2skip
v0.t=0, not executed
--
i=3active
uint_to_float(3)
3
i=4active
uint_to_float(7)
7
i=5active
uint_to_float(8)
8
i=6skip
v0.t=0, not executed
--
i=7active
uint_to_float(31)
31
SEW=32 / binary32 demo values convert unsigned integer elements to same-SEW FP results; dynamic frm is used when rounding is required, and this animation shows RNE. To avoid JavaScript precision ambiguity, editable inputs are limited to small checkable integer samples.
The teaching context fixes VLEN=4096, LMUL=m1, vstart=0, enabled VS/FS, and supported SEW. FP inputs are first represented as binary32/64. VL=0 updates no destination elements; same-width source/destination overlap is allowed. Inactive and tail values follow ma/ta without definite displayed values.
Quick Understanding & Search Notes
VFCVT.F.XU.V is best understood as a VFUNARY0 single-width conversion: after decoding vs1=00010, active elements convert vs2[i] from an unsigned integer to FP.
In the OP-V encoding, funct6=010010 and funct3=001 select the vector FP/integer conversion group, and vs1=00010 selects VFCVT.F.XU.V.
The syntax input contains only vd, vs2, and vm; VL, SEW, frm, v0.t, and element values are execution context.
This is a single-width conversion, so input and output both use the current SEW.
When rounding is required, the floating-point dynamic rounding mode frm is used.
Only active elements within vl execute; vm=0 uses v0.t and vm=1 is unmasked.
Integer-to-FP conversion rounds using frm and sets inexact when the result differs from the source integer and invalid is not set. Source integers are neither NaNs nor infinities.
This animation demonstrates SEW=32/64. These single-width conversions at SEW=16 require Zvfh; Zvfhmin alone adds only FP widening/narrowing conversions between binary16 and binary32.
Vector Execution Context
vd and vs2 are SEW-wide vector groups; same-EEW source/destination overlap is allowed. VFADD.VV also reads a SEW-wide vs1 vector, and equal source registers read equal initial values. Unary instructions use the encoded vs1 bits as a fixed selector.
Require V, enabled VS/FS and supported vtype. V supports binary32/64; these instructions at SEW=16 require Zvfh, not Zvfhmin alone. FS=Off raises illegal instruction; with H and V=1, vsstatus.FS/VS must also be enabled.
Active elements satisfy vstart≤i<vl and (vm=1 or v0[i]=1); omitting v0.t means vm=1. Prestart elements are unchanged, and inactive/tail elements follow vma/vta. VL=0 or vstart≥vl leaves the entire destination unchanged; successful completion resets vstart=0. Implementations may reject nonzero vstart values they cannot produce.
Masked vd cannot overlap v0; v0 cannot supply both an EEW=1 mask and SEW data source. Invalid frm use is reserved even without rounding, at VL=0 or vstart≥vl; an illegal-instruction exception is not guaranteed by that rule.
Dynamic frm controls rounding; only active-element FP exceptions accrue in fflags. Fixed-point vxrm is not used. Integer-to-FP conversion is numeric, not a bit move, and inexact conversion sets NX.
Common Usage Scenarios
Integer data to FP vectors
Assume V/VS/FS enabled, frm=RNE, vstart=0, supported e32,m1, VLMAX≥4 and a0=4. The example is unmasked, so all four body elements execute. Initial values and results: v2=[0,1,3,15] → v1=[0,1,3,15]. Conversion results use the destination integer/FP type; tails follow ta without assumed zeroing.
Mixed-type vector math
Assume V/VS/FS enabled, frm=RNE, vstart=0, supported e32,m1, VLMAX≥4 and a0=4. The example is unmasked, so all four body elements execute. Initial values and results: v2=[0,1,3,15] → v1=[0,1,3,15]. Conversion results use the destination integer/FP type; tails follow ta without assumed zeroing.
Vectorized numeric preparation
Assume V/VS/FS enabled, frm=RNE, vstart=0, supported e32,m1, VLMAX≥4 and a0=4. The example is unmasked, so all four body elements execute. Initial values and results: v2=[0,1,3,15] → v1=[0,1,3,15]. Conversion results use the destination integer/FP type; tails follow ta without assumed zeroing.
Pre-Use Checklist
Syntax Check
- vd and vs2 are SEW-wide vector groups; same-EEW source/destination overlap is allowed. VFADD.VV also reads a SEW-wide vs1 vector, and equal source registers read equal initial values. Unary instructions use the encoded vs1 bits as a fixed selector.
- Require V, enabled VS/FS and supported vtype. V supports binary32/64; these instructions at SEW=16 require Zvfh, not Zvfhmin alone. FS=Off raises illegal instruction; with H and V=1, vsstatus.FS/VS must also be enabled.
Semantic Check
- Active elements satisfy vstart≤i<vl and (vm=1 or v0[i]=1); omitting v0.t means vm=1. Prestart elements are unchanged, and inactive/tail elements follow vma/vta. VL=0 or vstart≥vl leaves the entire destination unchanged; successful completion resets vstart=0. Implementations may reject nonzero vstart values they cannot produce.
- Masked vd cannot overlap v0; v0 cannot supply both an EEW=1 mask and SEW data source. Invalid frm use is reserved even without rounding, at VL=0 or vstart≥vl; an illegal-instruction exception is not guaranteed by that rule.
- Dynamic frm controls rounding; only active-element FP exceptions accrue in fflags. Fixed-point vxrm is not used. Integer-to-FP conversion is numeric, not a bit move, and inexact conversion sets NX.
Pitfalls / Common Confusions
This is a single-width conversion: input and output both use the current SEW; do not treat it as a VFWCVT widening or VFNCVT narrowing form.
When rounding is required, it uses floating-point frm; do not confuse this with the fixed-point rounding mode vxrm.
VFCVT.F.XU.V interprets source elements as unsigned integers before converting them to FP; it is not an FP bit-pattern move.
With vm=0, v0.t selects active elements only; masked-off elements do not produce the conversion result shown by the animation.
Integer-to-FP conversion has no NaN or infinity source operand; inexact results and rounding behavior follow the official FP conversion rules, while the page animation demonstrates small, checkable integer examples.
Do not read the SEW=32/64 animation examples as a complete SEW=16 half-precision simulator; these SEW=16 single-width conversions require Zvfh; Zvfhmin alone adds only FP widening/narrowing conversions between binary16 and binary32.
FAQ
Where does VFCVT.F.XU.V take its rounding mode from?
When rounding is required, it uses the floating-point dynamic rounding mode frm, not the fixed-point vxrm.
How does VFCVT.F.XU.V use the mask operand?
With vm=0, only active elements selected by v0.t are converted; vm=1 is unmasked. Inactive and tail elements follow the current vma/vta policies.