Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VFWCVT.F.XU.V
RISC-V VFWCVT.F.XU.V Instruction Details
Instruction ManualR-typeVFWCVT.F.XU.V widens each active vs2[i] from an SEW-wide unsigned integer value to a 2*SEW-wide FP result and writes vd[i].
Instruction Syntax
vfwcvt.f.xu.v vd, vs2, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VZvfhVector Type ConvertFloating-Point
Instruction Behavior
VFWCVT.F.XU.V is a RISC-V V-extension VFWCVT widening floating-point/integer conversion instruction with syntax vfwcvt.f.xu.v vd, vs2, vm. It executes only for active elements within vl, uses the current SEW for source elements, and writes 2*SEW-wide destination elements; on the base V FP32/FP64 path, this page animation demonstrates SEW=32 inputs producing 64-bit destination results. The encoding uses OP-V, funct6=010010, funct3=001, and VFUNARY0 vs1 selector 01010. When rounding is required, the floating-point dynamic rounding mode frm is used; this page animation uses RNE as a checkable example; vm=0 uses v0.t as the execution mask and vm=1 is unmasked.
VFWCVT.F.XU.V Decode And Execute Animation
Decode the OP-V encoding and execute a VFUNARY0 widening conversion lane by lane: each active lane converts the unsigned integer in vs2[i] to a 2*SEW FP value.
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Instruction input
vfwcvt.f.xu.v
Execution context
frm
RNE
demo dynamic rounding modedest EEW
64
destination element widthvta/vma
ta, ma
tail/inactive policyopcode
1010111
OP-V major opcodevs1
01010
VFUNARY0 conversion selectorEncoding fields
0x48851257
31..26
25
24..20
19..15
14..12
11..7
6..0
010010
funct6
0
vm
01000
vs2
01010
vs1/sel
001
funct3
00100
vd
1010111
OP-V
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
widen_uint_to_float(0)
0
i=1active
widen_uint_to_float(1)
1
i=2skip
v0.t=0, not executed
--
i=3active
widen_uint_to_float(3)
3
i=4active
widen_uint_to_float(7)
7
i=5active
widen_uint_to_float(8)
8
i=6skip
v0.t=0, not executed
--
i=7active
widen_uint_to_float(31)
31
source SEW=32 integer -> destination binary64 demo values convert unsigned integer elements to 2*SEW FP results; dynamic frm is used when rounding is required, and this animation shows RNE. To avoid JavaScript precision ambiguity, editable inputs are limited to small checkable integer samples.
Quick Understanding & Search Notes
VFWCVT.F.XU.V is best understood as a VFUNARY0 widening conversion: after decoding vs1=01010, active elements convert vs2[i] from an SEW-wide unsigned integer value to a 2*SEW-wide FP result.
In the OP-V encoding, funct6=010010 and funct3=001 select the vector FP/integer conversion group, and VFUNARY0 vs1=01010 selects VFWCVT.F.XU.V.
The syntax input contains only vd, vs2, and vm; VL, SEW, frm, v0.t, and element values are execution context.
This is a widening conversion: source elements use the current SEW and destination elements use 2*SEW; the common base-V path is SEW=32 input producing a 64-bit destination result.
When rounding is required, the floating-point dynamic rounding mode frm is used; this page animation uses RNE as a checkable example.
Only active elements within vl execute; vm=0 uses v0.t and vm=1 is unmasked.
Widening instructions obey the official widening register-overlap constraints; this page animation uses an even vd to represent the vd..vd+1 destination group for LMUL=1.
Integer-to-FP conversions can round according to frm and set inexact when the FP result differs from the integer value; they do not have NaN or infinity source operands.
SEW=16 half-precision or BF16-related extension forms are not fully simulated by this page animation and remain governed by the official Zvfh/Zvfhmin/Zvfbf* rules.
Vector Execution Context
When reading VFWCVT.F.XU.V, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
integer vectors promoted to binary64 FP
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfwcvt.f.xu.v v2, v4».
mixed-precision vector compute entry
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfwcvt.f.xu.v v2, v4».
FP paths preserving 32-bit integer precision
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfwcvt.f.xu.v v2, v4».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
This is a widening VFWCVT form: the source is SEW and the destination is 2*SEW; do not treat it as single-width VFCVT or narrowing VFNCVT.
The destination register group occupies the wider EMUL result; this LMUL=1 page animation requires an even vd and avoids vd..vd+1 overlap with the source group.
With vm=0, v0.t selects active elements only; masked-off elements do not produce the conversion result shown by the animation.
Integer-to-FP source operands are not NaN or infinity; when rounding is required it follows frm, and inexact can be set when the FP result differs from the integer value.
This page animation covers the checkable SEW=32 to 64-bit destination path; SEW=16/Zvfh/Zvfhmin or BF16-related forms remain governed by the official extension rules.
FAQ
How is VFWCVT.F.XU.V different from VFCVT?
VFWCVT.F.XU.V is a VFWCVT widening form: the source is SEW and the destination is 2*SEW. Single-width VFCVT uses the current SEW for both source and destination.
Where does VFWCVT.F.XU.V take its rounding mode from?
When rounding is required, it uses the floating-point dynamic rounding mode frm, not the fixed-point vxrm.
How does VFWCVT.F.XU.V use the mask operand?
With vm=0, only active elements selected by v0.t are converted; vm=1 is unmasked. Inactive and tail elements follow the current vma/vta policy.
Why does this page animation expose only SEW=32?
The animation focuses on the most checkable base-V FP32/FP64 widening path: SEW=32 input and 2*SEW=64 destination. SEW=16 half precision, 8-bit integer-to-binary16, and BF16-related forms are defined by their corresponding official extensions.