Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VFCLASS.V
RISC-V VFCLASS.V Instruction Details
Instruction ManualR-typeClassifies each active FP element with the official FCLASS 10-class table and writes the one-hot class code to the low bits of vd[i].
Instruction Syntax
vfclass.v vd, vs2, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VZvfhVector OperationsFloating-Point
Instruction Behavior
VFCLASS.V is an RVV unary FP classify instruction with syntax vfclass.v vd, vs2, vm; each active element reads the FP encoding of vs2[i] and writes a 10-bit one-hot class code to the low bits of the ordinary vector data element vd[i], with upper bits zero. Code bits 0..9 represent negative infinity, negative normal, negative subnormal, negative zero, positive zero, positive subnormal, positive normal, positive infinity, signaling NaN, and quiet NaN.
VFCLASS.V Decode And Execute Animation
Decode the OP-V encoding and execute VFUNARY1 FP classify lane by lane: each active lane reads the raw vs2[i] FP encoding and writes a 10-bit one-hot class code.
Step 1 / 23
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Instruction input
vfclass.v
Execution context
frm
RNE
not rounded by frmvta/vma
ta, ma
tail/inactive policyopcode
1010111
OP-V major opcodevs1
10000
VFUNARY1 classify selectorEncoding fields
0x4c881257
31..26
25
24..20
19..15
14..12
11..7
6..0
010011
funct6
0
vm
01000
vs2
10000
vs1/class
001
funct3
00100
vd
1010111
OP-V
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
class(0xff800000) bit0
0x001 (-infinity)
i=1active
class(0xc0200000) bit1
0x002 (-normal)
i=2skip
v0.t=0, not executed
--
i=3active
class(0x80000000) bit3
0x008 (-zero)
i=4active
class(0x00000000) bit4
0x010 (+zero)
i=5active
class(0x00000001) bit5
0x020 (+subnormal)
i=6skip
v0.t=0, not executed
--
i=7active
class(0x7f800000) bit7
0x080 (+infinity)
i=8active
class(0x7f800001) bit8
0x100 (signaling NaN)
i=9active
class(0x7fc00000) bit9
0x200 (quiet NaN)
i=10skip
v0.t=0, not executed
--
i=11active
class(0xc0200000) bit1
0x002 (-normal)
i=12active
class(0x80000001) bit2
0x004 (-subnormal)
i=13active
class(0x80000000) bit3
0x008 (-zero)
i=14skip
v0.t=0, not executed
--
i=15active
class(0x00000001) bit5
0x020 (+subnormal)
SEW=32 / binary32 demo values show the official FCLASS 10-class one-hot code: bits 0..9 represent -inf, -normal, -subnormal, -0, +0, +subnormal, +normal, +inf, sNaN, and qNaN. Classification is not rounded and does not set fflags.
Quick Understanding & Search Notes
VFCLASS.V does not produce an FP value or Boolean mask; it maps each active FP element to the official 10-class one-hot integer class code.
In the OP-V encoding, funct6=010011 and funct3=001 select the VFUNARY1 FP unary class group, and the vs1 field is fixed to 10000 for VFCLASS.
Only active elements within vl execute; vm=0 uses v0.t as the execution mask and vm=1 is unmasked.
The 10-bit one-hot class code bits 0..9 cover -inf, -normal, -subnormal, -0, +0, +subnormal, +normal, +inf, sNaN, and qNaN.
The class result is written to the low bits of ordinary vector data elements, with upper bits zero; VFCLASS performs no rounding and sets no fflags.
Vector Execution Context
When reading VFCLASS.V, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Numeric Classification
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfclass.v v1, v2».
NaN / Infinity Tests
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfclass.v v1, v2».
Vectorized Data Cleaning
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfclass.v v1, v2».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
The result is written to ordinary vector data elements, not to a one-bit-per-element mask register.
The result is a 10-bit one-hot class code; do not treat it as a VMFEQ/VMFNE-style 0/1 compare result.
The encoded vs1 field is fixed to 10000 to select VFCLASS; the assembly syntax has no second source vector.
VFCLASS.V performs no numeric rounding and does not set FP exception flags.
FAQ
Is the VFCLASS.V result a mask?
No. It writes a 10-bit one-hot class code into ordinary vector data elements; this differs from the one-bit mask result produced by VMFEQ/VMFNE.
Does VFCLASS.V set invalid for NaN inputs?
No. The official FCLASS semantics state that classification does not set FP exception flags, including for signaling NaN or quiet NaN inputs.
What is vs1 in VFCLASS.V?
The assembly syntax has only vd, vs2, and vm; the encoded vs1 field is fixed to 10000 to select classify inside the VFUNARY1 space.