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VFCLASS.V

RISC-V VFCLASS.V Instruction Details

Instruction ManualOPFVV

Classifies each active FP element with the official FCLASS 10-class table and writes the one-hot class code to the low bits of vd[i].

Instruction Syntax

vfclass.v vd, vs2, vm
Operand Breakdown
vd and vs2 are SEW-wide vector groups; same-EEW source/destination overlap is allowed. VFADD.VV also reads a SEW-wide vs1 vector, and equal source registers read equal initial values. Unary instructions use the encoded vs1 bits as a fixed selector.
Require V, enabled VS/FS and supported vtype. V supports binary32/64; these instructions at SEW=16 require Zvfh, not Zvfhmin alone. FS=Off raises illegal instruction; with H and V=1, vsstatus.FS/VS must also be enabled.
Active elements satisfy vstart≤i<vl and (vm=1 or v0[i]=1); omitting v0.t means vm=1. Prestart elements are unchanged, and inactive/tail elements follow vma/vta. VL=0 or vstart≥vl leaves the entire destination unchanged; successful completion resets vstart=0. Implementations may reject nonzero vstart values they cannot produce.
Masked vd cannot overlap v0; v0 cannot supply both an EEW=1 mask and SEW data source. Invalid frm use is reserved even without rounding, at VL=0 or vstart≥vl; an illegal-instruction exception is not guaranteed by that rule.
The class code occupies the low 10 bits of vd[i], with upper bits zero and exactly one bit set. Even sNaN/qNaN classification sets no fflags.
VVector OperationsFloating-Point
Related Search Terms
vfclass.v instructionRISC-V vfclass.vvfclass.v syntaxvfclass.v encodingvfclass.v class codeRVV FP classifyvfclass.v NaN classvector FCLASS

Instruction Behavior

VFCLASS.V is an RVV unary FP classify instruction with syntax vfclass.v vd, vs2, vm; each active element reads the FP encoding of vs2[i] and writes a 10-bit one-hot class code to the low bits of the ordinary vector data element vd[i], with upper bits zero. Code bits 0..9 represent negative infinity, negative normal, negative subnormal, negative zero, positive zero, positive subnormal, positive normal, positive infinity, signaling NaN, and quiet NaN.

VFCLASS.V Decode And Execute Animation

Decode the OP-V encoding and execute VFUNARY1 FP classify lane by lane: each active lane reads the raw vs2[i] FP encoding and writes a 10-bit one-hot class code.

Instruction input
vfclass.v
Execution context
LMULm1fixed register-group multiplier
VLEN4096fixed vector-register length (bits)
VLMAX128maximum element count at m1
vstart0prestart elements are outside this animation
frmRNEnot rounded by frm
FP stateFS enabledFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled
vta/vmata, matail/inactive policy
opcode1010111OP-V major opcode
vs110000VFUNARY1 classify selector
Encoding fields
0x4c881257
31..26
25
24..20
19..15
14..12
11..7
6..0
010011
funct6
0
vm
01000
vs2
10000
vs1/class
001
funct3
00100
vd
1010111
OP-V
Execution data path

lane 0: class(0xff800000) bit0 -> 0x001 (-infinity)

This lane follows the current-step highlight; the remaining lane results appear below.

Step 1 / 23
Read OP-V encoding fields

V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.

Lane results
Long vectors scroll inside this module without page overflow.
i=0active
class(0xff800000) bit0
0x001 (-infinity)
i=1active
class(0xc0200000) bit1
0x002 (-normal)
i=2skip
v0.t=0, not executed
--
i=3active
class(0x80000000) bit3
0x008 (-zero)
i=4active
class(0x00000000) bit4
0x010 (+zero)
i=5active
class(0x00000001) bit5
0x020 (+subnormal)
i=6skip
v0.t=0, not executed
--
i=7active
class(0x7f800000) bit7
0x080 (+infinity)
i=8active
class(0x7f800001) bit8
0x100 (signaling NaN)
i=9active
class(0x7fc00000) bit9
0x200 (quiet NaN)
i=10skip
v0.t=0, not executed
--
i=11active
class(0xc0200000) bit1
0x002 (-normal)
i=12active
class(0x80000001) bit2
0x004 (-subnormal)
i=13active
class(0x80000000) bit3
0x008 (-zero)
i=14skip
v0.t=0, not executed
--
i=15active
class(0x00000001) bit5
0x020 (+subnormal)
SEW=32 / binary32 demo values show the official FCLASS 10-class one-hot code: bits 0..9 represent -inf, -normal, -subnormal, -0, +0, +subnormal, +normal, +inf, sNaN, and qNaN. Classification is not rounded and does not set fflags.

The teaching context fixes VLEN=4096, LMUL=m1, vstart=0, enabled VS/FS, and supported SEW. FP inputs are first represented as binary32/64. VL=0 updates no destination elements; same-width source/destination overlap is allowed. Inactive and tail values follow ma/ta without definite displayed values.

Quick Understanding & Search Notes

VFCLASS.V does not produce an FP value or Boolean mask; it maps each active FP element to the official 10-class one-hot integer class code.

In the OP-V encoding, funct6=010011 and funct3=001 select the VFUNARY1 FP unary class group, and the vs1 field is fixed to 10000 for VFCLASS.
Only active elements within vl execute; vm=0 uses v0.t as the execution mask and vm=1 is unmasked.
The 10-bit one-hot class code bits 0..9 cover -inf, -normal, -subnormal, -0, +0, +subnormal, +normal, +inf, sNaN, and qNaN.
The class result is written to the low bits of ordinary vector data elements, with upper bits zero; VFCLASS performs no rounding and sets no fflags.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120

Vector Execution Context

vd and vs2 are SEW-wide vector groups; same-EEW source/destination overlap is allowed. VFADD.VV also reads a SEW-wide vs1 vector, and equal source registers read equal initial values. Unary instructions use the encoded vs1 bits as a fixed selector.

Require V, enabled VS/FS and supported vtype. V supports binary32/64; these instructions at SEW=16 require Zvfh, not Zvfhmin alone. FS=Off raises illegal instruction; with H and V=1, vsstatus.FS/VS must also be enabled.

Active elements satisfy vstart≤i<vl and (vm=1 or v0[i]=1); omitting v0.t means vm=1. Prestart elements are unchanged, and inactive/tail elements follow vma/vta. VL=0 or vstart≥vl leaves the entire destination unchanged; successful completion resets vstart=0. Implementations may reject nonzero vstart values they cannot produce.

Masked vd cannot overlap v0; v0 cannot supply both an EEW=1 mask and SEW data source. Invalid frm use is reserved even without rounding, at VL=0 or vstart≥vl; an illegal-instruction exception is not guaranteed by that rule.

The class code occupies the low 10 bits of vd[i], with upper bits zero and exactly one bit set. Even sNaN/qNaN classification sets no fflags.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, Chapter 31

Common Usage Scenarios

Numeric Classification

Assume V/VS/FS enabled, frm=RNE, vstart=0, supported e32,m1, VLMAX≥4 and a0=4. The example is unmasked, so all four body elements execute. Initial values and results: v2=[-0,+0,-2.5,+∞] → v1=[0x008,0x010,0x002,0x080]. Conversion results use the destination integer/FP type; tails follow ta without assumed zeroing.

NaN / Infinity Tests

Assume V/VS/FS enabled, frm=RNE, vstart=0, supported e32,m1, VLMAX≥4 and a0=4. The example is unmasked, so all four body elements execute. Initial values and results: v2=[-0,+0,-2.5,+∞] → v1=[0x008,0x010,0x002,0x080]. Conversion results use the destination integer/FP type; tails follow ta without assumed zeroing.

Vectorized Data Cleaning

Assume V/VS/FS enabled, frm=RNE, vstart=0, supported e32,m1, VLMAX≥4 and a0=4. The example is unmasked, so all four body elements execute. Initial values and results: v2=[-0,+0,-2.5,+∞] → v1=[0x008,0x010,0x002,0x080]. Conversion results use the destination integer/FP type; tails follow ta without assumed zeroing.

Pre-Use Checklist

Syntax Check
  • vd and vs2 are SEW-wide vector groups; same-EEW source/destination overlap is allowed. VFADD.VV also reads a SEW-wide vs1 vector, and equal source registers read equal initial values. Unary instructions use the encoded vs1 bits as a fixed selector.
  • Require V, enabled VS/FS and supported vtype. V supports binary32/64; these instructions at SEW=16 require Zvfh, not Zvfhmin alone. FS=Off raises illegal instruction; with H and V=1, vsstatus.FS/VS must also be enabled.
Semantic Check
  • Active elements satisfy vstart≤i<vl and (vm=1 or v0[i]=1); omitting v0.t means vm=1. Prestart elements are unchanged, and inactive/tail elements follow vma/vta. VL=0 or vstart≥vl leaves the entire destination unchanged; successful completion resets vstart=0. Implementations may reject nonzero vstart values they cannot produce.
  • Masked vd cannot overlap v0; v0 cannot supply both an EEW=1 mask and SEW data source. Invalid frm use is reserved even without rounding, at VL=0 or vstart≥vl; an illegal-instruction exception is not guaranteed by that rule.
  • The class code occupies the low 10 bits of vd[i], with upper bits zero and exactly one bit set. Even sNaN/qNaN classification sets no fflags.

Pitfalls / Common Confusions

The result is written to ordinary vector data elements, not to a one-bit-per-element mask register.
The result is a 10-bit one-hot class code; do not treat it as a VMFEQ/VMFNE-style 0/1 compare result.
The encoded vs1 field is fixed to 10000 to select VFCLASS; the assembly syntax has no second source vector.
VFCLASS.V performs no numeric rounding and does not set FP exception flags.

FAQ

Is the VFCLASS.V result a mask?

No. It writes a 10-bit one-hot class code into ordinary vector data elements; this differs from the one-bit mask result produced by VMFEQ/VMFNE.

Does VFCLASS.V set invalid for NaN inputs?

No. The official FCLASS semantics state that classification does not set FP exception flags, including for signaling NaN or quiet NaN inputs.

What is vs1 in VFCLASS.V?

The assembly syntax has only vd, vs2, and vm; the encoded vs1 field is fixed to 10000 to select classify inside the VFUNARY1 space.