Does VMFNE.VV write ordinary vector elements?
No. VMFNE.VV writes mask destination vd, producing one Boolean bit for each active element.
VMFNE.VV
RISC-V VMFNE.VV Instruction Details
Instruction ManualOP-V (OPFVV)Perform lane-wise FP not-equal comparison and write Boolean results to mask destination vd.
Instruction Syntax
vmfne.vv vd, vs2, vs1[, v0.t]
Operand Breakdown
Active elements compute vs2[i] != vs1[i] into bit i of one mask register. Either NaN produces 1; only sNaN raises NV. +0/-0 compare equal; inactive elements raise no NV.
32-bit OP-V: opcode=1010111, funct6=011100, funct3=001. [, v0.t] is optional: omitted means vm=1; included means vm=0.
The mask destination may be v0. Different-EEW destination/source overlap must start at the source group's lowest register and forces ma/ta. Masked data sources cannot be v0. Equal vector sources require equal initial bits.
Require V 1.0, valid vtype, enabled VS, and supported SEW, plus enabled FS, supported FP formats, and valid frm even though comparison does not round. Body is vstart≤i<vl; prestart is unchanged, inactive elements follow vma, and mask tails are always agnostic. vl=0 or vstart≥vl updates no destination, including tails. The animation fixes m1, VLEN=4096, and vstart=0; steps are not processor cycles.
VVector FPCompare
Instruction Behavior
VMFNE.VV is a RISC-V V-extension vector floating-point compare instruction. For active elements within vl, it evaluates vs2[i] != same-lane vs1[i] and writes each Boolean result to the corresponding bit of mask destination vd. vm=0 uses v0.t as the execution mask and vm=1 is unmasked; NaN handling, invalid exception flags, and tail-agnostic result rules follow the official RVV FP compare semantics.
VMFNE.VV Decode And Execute Animation
Decode the OP-V encoding and execute lane-wise FP compare: each active lane evaluates vs2[i] != vs1[i] and writes the Boolean result to the destination mask bit.
Instruction input
vmfne.vv
Execution context
LMULfixed register-group multiplier
VLENfixed vector-register length (bits)
VLMAXmaximum element count at m1
vstartprestart elements are outside this animation
frmnot rounded by frm
FP stateFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled
vta/vmatail/inactive policy
opcodeOP-V major opcode
Encoding fields
0x70861257
31..26
25
24..20
19..15
14..12
11..7
6..0
011100
funct6
0
vm
01000
vs2
01100
vs1
001
funct3
00100
vd
1010111
OP-V
Execution data path
lane 0: 1 != 0.5 -> mask=1
This lane follows the current-step highlight; the remaining lane results appear below.
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Lane results
This execution does not raise NVLong vectors scroll inside this module without page overflow.
i=0active
1 != 0.5
mask=1
i=1active
1.5 != 1
mask=1
i=2skip
v0.t=0, not executed
--
i=3active
2.5 != 2
mask=1
i=4active
-3 != 2.5
mask=1
i=5active
3.5 != 3
mask=1
i=6skip
v0.t=0, not executed
--
i=7active
4.5 != 4
mask=1
The teaching context fixes VLEN=4096, LMUL=m1, vstart=0, valid vtype, enabled VS/FS, valid frm=RNE, and ta/ma, with the selected binary32/64 supported. Both vector sources have the same width; equal source registers require equal initial bits. vd is a single mask register, may be v0, and may start at a data source; legal different-EEW overlap forces mask/tail agnostic. Masked data sources cannot be v0 because one register cannot supply both EEW=1 mask and SEW data. Inactive bits have no definite displayed value; mask tails are always agnostic. VL=0 updates no destination bits. NV shows only what this execution raises and does not clear old fflags. Comparison does not round by frm, but invalid frm use remains reserved. Steps are not processor cycles.
SEW=32 / binary32 demo accepts finite values or full IEEE hexadecimal bit patterns, so qNaN/sNaN can be checked. Active lanes write 0/1 destination mask bits and show this execution's fflags.NV when required. Officially, VMFEQ/VMFNE raise invalid only for signaling NaN inputs; VMFLT/VMFLE/VMFGT/VMFGE raise invalid for signaling or quiet NaN inputs; VMFNE writes 1 when either operand is NaN, while the other compares write 0.Quick Understanding & Search Notes
VMFNE.VV is best understood by decoding the OP-V vv form, evaluating vs2[i] != same-lane vs1[i] for active elements, and writing true/false as destination mask bits.
In the OP-V encoding, funct6=011100 and funct3=001 select the vv FP compare form for VMFNE.VV.
Active elements evaluate vs2[i] != same-lane vs1[i]; the result is written to bit i of mask destination vd.
vm=0 uses v0.t as the execution mask; vm=1 is unmasked.
Compare instructions write mask results, and tail elements are tail-agnostic.
The official V specification allows a mask-producing compare destination mask to overlap source mask v0.
VMFEQ/VMFNE raise invalid only for signaling NaN inputs; VMFLT/VMFLE/VMFGT/VMFGE raise invalid for signaling or quiet NaN inputs.
Except for VMFNE, which writes 1 when either operand is NaN, FP compares write 0 for NaN comparisons.
Body is vstart≤i<vl; inactive bits follow vma and mask tails are always agnostic. vl=0 or vstart≥vl updates no destination bits.
Require valid vtype, enabled VS/FS, supported FP formats, and valid frm. Comparison does not round, but invalid frm use is reserved.
Vector Execution Context
Active elements compute vs2[i] != vs1[i] into bit i of one mask register. Either NaN produces 1; only sNaN raises NV. +0/-0 compare equal; inactive elements raise no NV.
32-bit OP-V: opcode=1010111, funct6=011100, funct3=001. [, v0.t] is optional: omitted means vm=1; included means vm=0.
The mask destination may be v0. Different-EEW destination/source overlap must start at the source group's lowest register and forces ma/ta. Masked data sources cannot be v0. Equal vector sources require equal initial bits.
Require V 1.0, valid vtype, enabled VS, and supported SEW, plus enabled FS, supported FP formats, and valid frm even though comparison does not round. Body is vstart≤i<vl; prestart is unchanged, inactive elements follow vma, and mask tails are always agnostic. vl=0 or vstart≥vl updates no destination, including tails. The animation fixes m1, VLEN=4096, and vstart=0; steps are not processor cycles.
Common Usage Scenarios
Predicate mask generation
Assume RV32/RV64 V 1.0, enabled VS, valid e32,m1, VLEN≥128, vl=4, vstart=0, ta/ma, and initialized sources; FS enabled, frm=RNE, unmasked; v2=[1.5,-0,2,1.5], v4=[1.5,0,1.5,1.5] → v1.mask[0..3]=[0,0,1,0]. This execution raises no NV and does not clear old fflags; mask tails are always agnostic.
FP condition testing
Assume RV32/RV64 V 1.0, enabled VS, valid e32,m1, VLEN≥128, vl=4, vstart=0, ta/ma, and initialized sources; FS enabled, frm=RNE, unmasked; v2=[1.5,-0,2,1.5], v4=[1.5,0,1.5,1.5] → v1.mask[0..3]=[0,0,1,0]. This execution raises no NV and does not clear old fflags; mask tails are always agnostic.
Vectorized conditional execution
Assume RV32/RV64 V 1.0, enabled VS, valid e32,m1, VLEN≥128, vl=4, vstart=0, ta/ma, and initialized sources; FS enabled, frm=RNE, unmasked; v2=[1.5,-0,2,1.5], v4=[1.5,0,1.5,1.5] → v1.mask[0..3]=[0,0,1,0]. This execution raises no NV and does not clear old fflags; mask tails are always agnostic.
Pre-Use Checklist
Syntax Check
- Active elements compute vs2[i] != vs1[i] into bit i of one mask register. Either NaN produces 1; only sNaN raises NV. +0/-0 compare equal; inactive elements raise no NV.
- 32-bit OP-V: opcode=1010111, funct6=011100, funct3=001. [, v0.t] is optional: omitted means vm=1; included means vm=0.
Semantic Check
- The mask destination may be v0. Different-EEW destination/source overlap must start at the source group's lowest register and forces ma/ta. Masked data sources cannot be v0. Equal vector sources require equal initial bits.
- Require V 1.0, valid vtype, enabled VS, and supported SEW, plus enabled FS, supported FP formats, and valid frm even though comparison does not round. Body is vstart≤i<vl; prestart is unchanged, inactive elements follow vma, and mask tails are always agnostic. vl=0 or vstart≥vl updates no destination, including tails. The animation fixes m1, VLEN=4096, and vstart=0; steps are not processor cycles.
Pitfalls / Common Confusions
The result uses mask-register layout, one bit per element; it is not an ordinary integer vector of 0/-1 or 0/1 elements.
Compare instructions write a mask destination and treat tail elements as tail-agnostic; do not read tail bits as ordinary FP results.
With vm=0, v0.t is the execution mask; compare instructions allow the mask destination vd to overlap the source mask v0.
VMFNE.VV's second source is the same-lane vector element vs1[i]; this form has no scalar rs1 or f[rs1] operand.
NaN and invalid-flag behavior follows the official RVV FP compare rules, not integer comparison or JavaScript comparison semantics.
FAQ
Can VMFNE.VV write v0 when vm=0?
Yes. The official V specification allows mask-producing compare instructions to overlap the destination mask with source mask v0, unlike ordinary masked vector instructions.
What result does VMFNE.VV produce for NaN comparisons?
Only active comparisons process NaNs: VMFNE writes 1 for either NaN and raises NV only for sNaN.