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VMFLT.VV

RISC-V VMFLT.VV Instruction Details

Instruction ManualR-type

Perform lane-wise FP less-than comparison and write Boolean results to mask destination vd.

Instruction Syntax

vmflt.vv vd, vs2, vs1, vm
Operand Breakdown
vd: mask destination register, with one Boolean result bit per element.
vs2/vs1 or scalar source: compared at the current SEW.
vm: vm=0 uses v0 to restrict participating elements, and vm=1 is unmasked.
VVector FPCompare
Related Search Terms
VMFLT.VV instructionRISC-V VMFLT.VVvmflt.vv syntaxvmflt.vv encodingRVV FP compareRVV mask resultvmflt.vv NaNvmflt.vv v0.t

Instruction Behavior

VMFLT.VV is a RISC-V V-extension vector floating-point compare instruction. For active elements within vl, it evaluates vs2[i] < same-lane vs1[i] and writes each Boolean result to the corresponding bit of mask destination vd. vm=0 uses v0.t as the execution mask and vm=1 is unmasked; NaN handling, invalid exception flags, and tail-agnostic result rules follow the official RVV FP compare semantics.

VMFLT.VV Decode And Execute Animation

Decode the OP-V encoding and execute lane-wise FP compare: each active lane evaluates vs2[i] < vs1[i] and writes the Boolean result to the destination mask bit.

Step 1 / 15
Read OP-V encoding fields

V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.

Instruction input
vmflt.vv
Execution context
frm
RNE
not rounded by frm
vta/vma
ta, ma
tail/inactive policy
opcode
1010111
OP-V major opcode
Encoding fields
0x6c861257
31..26
25
24..20
19..15
14..12
11..7
6..0
011011
funct6
0
vm
01000
vs2
01100
vs1
001
funct3
00100
vd
1010111
OP-V
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
1 < 0.5
mask=0
i=1active
1.5 < 1
mask=0
i=2skip
v0.t=0, not executed
--
i=3active
2.5 < 2
mask=0
i=4active
-3 < 2.5
mask=1
i=5active
3.5 < 3
mask=0
i=6skip
v0.t=0, not executed
--
i=7active
4.5 < 4
mask=0
SEW=32 / binary32 demo values cover the finite compare path and write 0/1 destination mask bits for active elements. Officially, VMFEQ/VMFNE raise invalid only for signaling NaN inputs; VMFLT/VMFLE/VMFGT/VMFGE raise invalid for signaling or quiet NaN inputs; VMFNE writes 1 when either operand is NaN, while the other compares write 0.

Quick Understanding & Search Notes

VMFLT.VV is best understood by decoding the OP-V vv form, evaluating vs2[i] < same-lane vs1[i] for active elements, and writing true/false as destination mask bits.

In the OP-V encoding, funct6=011011 and funct3=001 select the vv FP compare form for VMFLT.VV.
Active elements evaluate vs2[i] < same-lane vs1[i]; the result is written to bit i of mask destination vd.
vm=0 uses v0.t as the execution mask; vm=1 is unmasked.
Compare instructions write mask results, and tail elements are tail-agnostic.
The official V specification allows a mask-producing compare destination mask to overlap source mask v0.
VMFEQ/VMFNE raise invalid only for signaling NaN inputs; VMFLT/VMFLE/VMFGT/VMFGE raise invalid for signaling or quiet NaN inputs.
Except for VMFNE, which writes 1 when either operand is NaN, FP compares write 0 for NaN comparisons.
RISC-V Unprivileged ISA Manual: V extension vector floating-point compare instructionsRISC-V Unprivileged ISA Manual: V extension mask and active-element rules

Vector Execution Context

When reading VMFLT.VV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vv: two vector sources participate element by element.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Predicate mask generation

Understand this scenario with real code like «vmflt.vv v1, v2, v4».

FP condition testing

Understand this scenario with real code like «vmflt.vv v1, v2, v4».

NaN checks

Understand this scenario with real code like «vmflt.vv v1, v2, v4».

Vectorized conditional execution

Understand this scenario with real code like «vmflt.vv v1, v2, v4».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

The result uses mask-register layout, one bit per element; it is not an ordinary integer vector of 0/-1 or 0/1 elements.
Compare instructions write a mask destination and treat tail elements as tail-agnostic; do not read tail bits as ordinary FP results.
With vm=0, v0.t is the execution mask; compare instructions allow the mask destination vd to overlap the source mask v0.
VMFLT.VV's second source is the same-lane vector element vs1[i]; this form has no scalar rs1 or f[rs1] operand.
NaN and invalid-flag behavior follows the official RVV FP compare rules, not integer comparison or JavaScript comparison semantics.

FAQ

Does VMFLT.VV write ordinary vector elements?

No. VMFLT.VV writes mask destination vd, producing one Boolean bit for each active element.

Can VMFLT.VV write v0 when vm=0?

Yes. The official V specification allows mask-producing compare instructions to overlap the destination mask with source mask v0, unlike ordinary masked vector instructions.

What result does VMFLT.VV produce for NaN comparisons?

VMFLT.VV writes 0 for NaN comparisons; invalid-flag behavior follows the official RVV FP compare definition.