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VMFLT.VV

RISC-V VMFLT.VV Instruction Details

Instruction ManualR-type

Perform element-wise < comparison and write the Boolean result to mask destination vd.

Instruction Syntax

vmflt.vv vd, vs2, vs1, vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
VVector FPCompare
Related Search Terms
VMFLT.VV instructionRISC-V VMFLT.VVvmflt.vv syntaxvmflt.vv RVVFP comparemask result

Instruction Behavior

VMFLT.VV is a RISC-V V vector floating-point compare instruction. For active elements within vl, it compares vs2 with vs1 and writes the comparison result to mask destination vd. NaN handling, invalid exception flags, and quiet/signaling comparison behavior follow RVV floating-point compare rules.

Quick Understanding & Search Notes

VMFLT.VV produces mask bits, not a 0/-1 integer vector.

The destination stores Boolean results in mask-register layout, one bit per element.
Floating-point comparisons follow RVV NaN and exception-flag rules; do not apply integer comparison semantics.
vm=0 uses v0 as the execution mask and vm=1 is unmasked; inactive and tail elements follow the current vma/vta policy.
RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations

Common Usage Scenarios

NaN Check

Understand this scenario with real code like «vmflt.vv v1, v2, v4».

Conditional Branch

Understand this scenario with real code like «vmflt.vv v1, v2, v4».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Result is mask register; tail always agnostic
NaN and invalid-flag behavior follows the RVV floating-point compare rules; do not apply integer compare semantics.
Vector FP32/FP64 compares require matching scalar F/D support; FP16 compare requires vector half-precision support.

FAQ

Does VMFLT.VV write ordinary vector elements?

No. Compare instructions write a mask destination vd, with one Boolean bit per element.

How does VMFLT.VV handle masking?

With vm=0, v0 selects active elements; with vm=1, all body elements participate. Inactive and tail elements follow the current policies.