Does VMFLE.VV write an FP vector?
No. Each active element writes one bit to mask vd.
VMFLE.VV
RISC-V VMFLE.VV Instruction Details
Instruction ManualOPFVVWrite active FP comparison results to mask vd.
Instruction Syntax
vmfle.vv vd, vs2, vs1[, v0.t]
Operand Breakdown
vd is one mask register: element i produces bit i, independent of SEW/LMUL, rather than a vector of SEW-bit 0/1 elements.
[, v0.t] denotes the optional execution mask: omitted means vm=1 and included means vm=0. Only active elements compare and raise NV; inactive/tail bits are not guaranteed zero.
The mask destination may be v0. Different-EEW destination/source overlap must start at the source group's lowest register and forces ma/ta. Masked data sources cannot also be v0. The animation fixes m1, so vd may equal a data source.
Require V 1.0, valid vtype, enabled VS/FS, supported FP width, and valid frm. vl=0 or vstart≥vl updates no destination bits. The animation fixes vstart=0 and VLEN=4096; steps are not processor cycles.
VVector FPCompare
Instruction Behavior
In V 1.0, active body elements write vs2[i] <= vs1[i] to vd.mask[i]. vm=0 uses v0.t; vm=1 is unmasked. NaNs produce 0.
VMFLE.VV Decode And Execute Animation
Decode the OP-V encoding and execute lane-wise FP compare: each active lane evaluates vs2[i] <= vs1[i] and writes the Boolean result to the destination mask bit.
Instruction input
vmfle.vv
Execution context
LMULfixed register-group multiplier
VLENfixed vector-register length (bits)
VLMAXmaximum element count at m1
vstartprestart elements are outside this animation
frmnot rounded by frm
FP stateFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled
vta/vmatail/inactive policy
opcodeOP-V major opcode
Encoding fields
0x64861257
31..26
25
24..20
19..15
14..12
11..7
6..0
011001
funct6
0
vm
01000
vs2
01100
vs1
001
funct3
00100
vd
1010111
OP-V
Execution data path
lane 0: 1 <= 0.5 -> mask=0
This lane follows the current-step highlight; the remaining lane results appear below.
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Lane results
This execution does not raise NVLong vectors scroll inside this module without page overflow.
i=0active
1 <= 0.5
mask=0
i=1active
1.5 <= 1
mask=0
i=2skip
v0.t=0, not executed
--
i=3active
2.5 <= 2
mask=0
i=4active
-3 <= 2.5
mask=1
i=5active
3.5 <= 3
mask=0
i=6skip
v0.t=0, not executed
--
i=7active
4.5 <= 4
mask=0
The teaching context fixes VLEN=4096, LMUL=m1, vstart=0, valid vtype, enabled VS/FS, valid frm=RNE, and ta/ma, with the selected binary32/64 supported. Both vector sources have the same width; equal source registers require equal initial bits. vd is a single mask register, may be v0, and may start at a data source; legal different-EEW overlap forces mask/tail agnostic. Masked data sources cannot be v0 because one register cannot supply both EEW=1 mask and SEW data. Inactive bits have no definite displayed value; mask tails are always agnostic. VL=0 updates no destination bits. NV shows only what this execution raises and does not clear old fflags. Comparison does not round by frm, but invalid frm use remains reserved. Steps are not processor cycles.
SEW=32 / binary32 demo accepts finite values or full IEEE hexadecimal bit patterns, so qNaN/sNaN can be checked. Active lanes write 0/1 destination mask bits and show this execution's fflags.NV when required. Officially, VMFEQ/VMFNE raise invalid only for signaling NaN inputs; VMFLT/VMFLE/VMFGT/VMFGE raise invalid for signaling or quiet NaN inputs; VMFNE writes 1 when either operand is NaN, while the other compares write 0.Quick Understanding & Search Notes
Active elements write (vs2[i] <= vs1[i]) to vd.mask[i].
32-bit OP-V: opcode=1010111, funct6=011001, funct3=001 (OPFVV).
Active elements evaluate vs2[i] <= vs1[i] and write vd.mask[i], not a SEW-bit integer or FP result.
Omitting v0.t gives vm=1; including it gives vm=0, comparing only body elements with v0.mask[i]=1.
Mask tails are always tail-agnostic, regardless of vta. Inactive bits follow vma; legal different-EEW source/destination overlap forces mask/tail agnostic.
The mask destination may be v0. A narrower destination must overlap at the source group’s lowest register; masked data sources cannot also be v0.
Only active elements raise flags; ordered comparison raises NV for either qNaN or sNaN. Either NaN produces 0, and +0 compares equal to -0.
Require V 1.0, enabled VS/FS, valid vtype, supported FP widths, and valid frm. Comparison does not round by frm, but invalid frm use remains reserved, including at vl=0.
Body is vstart≤i<vl; prestart is unchanged. With vl=0 or vstart≥vl, no destination bits, including tails, are updated; normal completion resets vstart=0 and leaves vl unchanged.
Vector Execution Context
vd is one mask register: element i produces bit i, independent of SEW/LMUL, rather than a vector of SEW-bit 0/1 elements.
[, v0.t] denotes the optional execution mask: omitted means vm=1 and included means vm=0. Only active elements compare and raise NV; inactive/tail bits are not guaranteed zero.
The mask destination may be v0. Different-EEW destination/source overlap must start at the source group's lowest register and forces ma/ta. Masked data sources cannot also be v0. The animation fixes m1, so vd may equal a data source.
Require V 1.0, valid vtype, enabled VS/FS, supported FP width, and valid frm. vl=0 or vstart≥vl updates no destination bits. The animation fixes vstart=0 and VLEN=4096; steps are not processor cycles.
Common Usage Scenarios
Generate FP comparison masks
Assume RV32/RV64 V 1.0, enabled VS/FS, valid e32,m1, VLEN≥128, vl=4, vstart=0, frm=RNE, ta/ma, and initialized sources; unmasked. v2=[1.5,-0,2,1.5], v4=[1.5,0,1.5,1.5] → v1.mask[0..3]=[1,1,0,1]; this execution raises no NV and does not clear old fflags. Tails are always agnostic.
Select compared elements with v0.t
Assume RV32/RV64 V 1.0, enabled VS/FS, valid e32,m1, VLEN≥128, vl=4, vstart=0, frm=RNE, ta/ma, and initialized sources; unmasked. v2=[1.5,-0,2,1.5], v4=[1.5,0,1.5,1.5] → v1.mask[0..3]=[1,1,0,1]; this execution raises no NV and does not clear old fflags. Tails are always agnostic.
Pre-Use Checklist
Syntax Check
- vd is one mask register: element i produces bit i, independent of SEW/LMUL, rather than a vector of SEW-bit 0/1 elements.
- [, v0.t] denotes the optional execution mask: omitted means vm=1 and included means vm=0. Only active elements compare and raise NV; inactive/tail bits are not guaranteed zero.
Semantic Check
- The mask destination may be v0. Different-EEW destination/source overlap must start at the source group's lowest register and forces ma/ta. Masked data sources cannot also be v0. The animation fixes m1, so vd may equal a data source.
- Require V 1.0, valid vtype, enabled VS/FS, supported FP width, and valid frm. vl=0 or vstart≥vl updates no destination bits. The animation fixes vstart=0 and VLEN=4096; steps are not processor cycles.
Pitfalls / Common Confusions
The result uses mask-register layout, one bit per element; it is not an ordinary integer vector of 0/-1 or 0/1 elements.
Compare instructions write a mask destination and treat tail elements as tail-agnostic; do not read tail bits as ordinary FP results.
With vm=0, v0.t is the execution mask; compare instructions allow the mask destination vd to overlap the source mask v0.
VMFLE.VV's second source is the same-lane vector element vs1[i]; this form has no scalar rs1 or f[rs1] operand.
Only active elements raise flags; ordered comparison raises NV for either qNaN or sNaN. Either NaN produces 0, and +0 compares equal to -0.
FAQ
Can VMFLE.VV write v0 with vm=0?
Yes. Mask-producing compares may overwrite source mask v0.
How does VMFLE.VV handle NaNs?
Only active elements raise flags; ordered comparison raises NV for either qNaN or sNaN. Either NaN produces 0, and +0 compares equal to -0.