What does the vm operand control for VFSQRT.V?
With vm=0, only active elements selected by v0.t execute; vm=1 is unmasked. The page formula is vd[i] = sqrt(vs2[i]).
VFSQRT.V
RISC-V VFSQRT.V Instruction Details
Instruction ManualOP-V / OPFVV VFUNARY1VFSQRT.V is an RVV single-width unary floating-point square-root instruction with syntax vfsqrt.v vd, vs2[, v0.t]; each active element computes vd[i] = sqrt(vs2[i]).
Instruction Syntax
vfsqrt.v vd, vs2[, v0.t]
Operand Breakdown
32-bit OP-V encoding: funct6=010011, funct3=001, opcode=1010111. vs1=00000 is a VFUNARY1 selector, not a second source register.
Read only vs2[i] and write sqrt(vs2[i]) to vd[i], rounded using dynamic frm. Active-element FP exceptions accrue in fflags; vxrm does not participate.
Vector operands and results have SEW bits and EMUL=LMUL. Same-width destination/source overlap is legal; equal sources require equal initial bits. An ordinary masked destination cannot overlap v0; one source register cannot be read as both an EEW=1 mask and SEW-wide data.
Optional assembly v0.t means vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled. Prestart elements do not update or raise exceptions. At vstart≥vl or vl=0 all destination elements, including tails, remain unchanged. Other inactive/tail elements follow vma/vta; ta/ma does not guarantee zeroing.
V supplies FP32/FP64 and depends on F/D; these operations at SEW=16 require Zvfh. Require the extensions, supported widths, valid vtype, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Every vector FP instruction requires valid frm, even without rounding or at vl=0; use of invalid frm is reserved.
The animation fixes VLEN=4096, LMUL=m1, vstart=0, valid frm=RNE, valid vtype, and enabled VS/FS. VF scalars use FLEN=64, assuming valid NaN-boxing at SEW=32. Steps are educational, not processor cycles; input and exception limits are stated in the animation.
VVector OperationsFloating-Point
Instruction Behavior
VFSQRT.V uses the OP-V VFUNARY1 form and has only vs2 and vm as source syntax operands; the encoded vs1 field selects the square-root operation and is not a user-written source register. An active finite negative input other than -0 produces a canonical NaN and sets NV; results, rounding, NaNs, infinities, and other exception flags follow the official RVV floating-point rules; fixed-point vxrm does not control this instruction. V defines SEW=32 and SEW=64; Zvfh is required only for SEW=16.
VFSQRT.V Decode And Execute Animation
Decode the OP-V encoding and execute the VFUNARY1 square-root operation lane by lane: each active lane computes sqrt(vs2[i]).
Instruction input
vfsqrt.v
Execution context
LMULfixed register-group multiplier
VLENfixed vector-register length (bits)
VLMAXmaximum element count at m1
vstartprestart elements are outside this animation
frmfinite teaching context fixed at RNE; the architectural instruction uses dynamic frm
FP stateFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled
vta/vmatail/inactive policy
opcodeOP-V major opcode
vs1VFUNARY1 square-root selector
Encoding fields
0x4c801257
31..26
25
24..20
19..15
14..12
11..7
6..0
010011
funct6
0
vm
01000
vs2
00000
vs1
001
funct3
00100
vd
1010111
OP-V
Execution data path
lane 0: sqrt(1) -> 0x3f800000 (1)
This lane follows the current-step highlight; the remaining lane results appear below.
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
sqrt(1)
0x3f800000 (1)
i=1active
sqrt(4)
0x40000000 (2)
i=2skip
v0.t=0, not executed
--
i=3active
sqrt(16)
0x40800000 (4)
i=4active
sqrt(25)
0x40a00000 (5)
i=5active
sqrt(36)
0x40c00000 (6)
i=6skip
v0.t=0, not executed
--
i=7active
sqrt(64)
0x41000000 (8)
The animation quantizes source values and results for the current SEW under the RNE demo mode: SEW=32 uses binary32 and SEW=64 uses binary64. NaN, infinity, and exception flags still follow the official RVV FP rules and are not expanded here as a full FP exception simulator.
The teaching context fixes VLEN=4096, LMUL=m1, vstart=0, valid vtype, enabled VS/FS, and valid frm=RNE, with the selected binary32/64 supported. Equal source registers require equal initial bits; same-width destination/source overlap is legal.VL=0 updates no destination elements, including tails; inactive and tail values follow ma/ta without definite displayed values. The animation accepts finite inputs and demonstrates RNE square root; negative inputs other than -0 return canonical NaN and show NV raised by this execution, while -0 retains its sign. NaN/infinity inputs, NX, and full accrued fflags are outside the model.
Quick Understanding & Search Notes
VFSQRT.V is unary vector FP square root: it reads only vs2 elements and writes sqrt(vs2[i]) to vd[i]; the encoded vs1 field is an operation selector, not a syntax source operand.
In the OP-V encoding, funct6=010011 and funct3=001 are used with vs1=00000 to select the VFUNARY1 square-root operation.
The semantic operation is vd[i] = sqrt(vs2[i]) for active elements within vl.
vm=0 uses v0.t as the execution mask; vm=1 is unmasked.
Rounding, negative inputs, NaNs, infinities, and fflags follow the official RVV FP rules; vxrm is not involved.
For ordinary masked vector instructions, the destination vector register group must not overlap the v0 mask source; the animation rejects vd=v0 when vm=0.
The optional assembly operand v0.t corresponds to vm=0; omitting it gives vm=1. Active elements satisfy vstart ≤ i < vl and the mask condition; VL=0 updates no destination elements, including tails.
Every vector FP instruction requires valid frm, including instructions that do not round and executions with VL=0; use of an invalid frm is reserved.
Vector Execution Context
32-bit OP-V encoding: funct6=010011, funct3=001, opcode=1010111. vs1=00000 is a VFUNARY1 selector, not a second source register.
Read only vs2[i] and write sqrt(vs2[i]) to vd[i], rounded using dynamic frm. Active-element FP exceptions accrue in fflags; vxrm does not participate.
Vector operands and results have SEW bits and EMUL=LMUL. Same-width destination/source overlap is legal; equal sources require equal initial bits. An ordinary masked destination cannot overlap v0; one source register cannot be read as both an EEW=1 mask and SEW-wide data.
Optional assembly v0.t means vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled. Prestart elements do not update or raise exceptions. At vstart≥vl or vl=0 all destination elements, including tails, remain unchanged. Other inactive/tail elements follow vma/vta; ta/ma does not guarantee zeroing.
V supplies FP32/FP64 and depends on F/D; these operations at SEW=16 require Zvfh. Require the extensions, supported widths, valid vtype, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Every vector FP instruction requires valid frm, even without rounding or at vl=0; use of invalid frm is reserved.
The animation fixes VLEN=4096, LMUL=m1, vstart=0, valid frm=RNE, valid vtype, and enabled VS/FS. VF scalars use FLEN=64, assuming valid NaN-boxing at SEW=32. Steps are educational, not processor cycles; input and exception limits are stated in the animation.
Common Usage Scenarios
Lane-wise square root
Assume V/VS/FS enabled, valid vtype, valid frm=RNE, supported e32,m1, VLMAX≥4, and a0=4; vsetvli sets vl=4 and vstart=0. Inputs are binary32; ft0, when used, is validly NaN-boxed at FLEN=64. Omitting v0.t makes this unmasked: v2=[1,4,9,16] → v1=[1,2,3,4]. Tails follow ta without assumed zeroing.
Vector norms
Assume V/VS/FS enabled, valid vtype, valid frm=RNE, supported e32,m1, VLMAX≥4, and a0=4; vsetvli sets vl=4 and vstart=0. Inputs are binary32; ft0, when used, is validly NaN-boxed at FLEN=64. Omitting v0.t makes this unmasked: v2=[1,4,9,16] → v1=[1,2,3,4]. Tails follow ta without assumed zeroing.
Numeric computing
Assume V/VS/FS enabled, valid vtype, valid frm=RNE, supported e32,m1, VLMAX≥4, and a0=4; vsetvli sets vl=4 and vstart=0. Inputs are binary32; ft0, when used, is validly NaN-boxed at FLEN=64. Omitting v0.t makes this unmasked: v2=[1,4,9,16] → v1=[1,2,3,4]. Tails follow ta without assumed zeroing.
Pre-Use Checklist
Syntax Check
- 32-bit OP-V encoding: funct6=010011, funct3=001, opcode=1010111. vs1=00000 is a VFUNARY1 selector, not a second source register.
- Read only vs2[i] and write sqrt(vs2[i]) to vd[i], rounded using dynamic frm. Active-element FP exceptions accrue in fflags; vxrm does not participate.
Semantic Check
- Vector operands and results have SEW bits and EMUL=LMUL. Same-width destination/source overlap is legal; equal sources require equal initial bits. An ordinary masked destination cannot overlap v0; one source register cannot be read as both an EEW=1 mask and SEW-wide data.
- Optional assembly v0.t means vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled. Prestart elements do not update or raise exceptions. At vstart≥vl or vl=0 all destination elements, including tails, remain unchanged. Other inactive/tail elements follow vma/vta; ta/ma does not guarantee zeroing.
- V supplies FP32/FP64 and depends on F/D; these operations at SEW=16 require Zvfh. Require the extensions, supported widths, valid vtype, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Every vector FP instruction requires valid frm, even without rounding or at vl=0; use of invalid frm is reserved.
- The animation fixes VLEN=4096, LMUL=m1, vstart=0, valid frm=RNE, valid vtype, and enabled VS/FS. VF scalars use FLEN=64, assuming valid NaN-boxing at SEW=32. Steps are educational, not processor cycles; input and exception limits are stated in the animation.
Pitfalls / Common Confusions
Syntax is vfsqrt.v vd, vs2[, v0.t]; do not add a vs1 or rs1 operand.
The encoded vs1=00000 is the VFUNARY1 square-root selector and does not mean v0 is read as an ordinary source vector.
Negative inputs, NaNs, infinities, rounding, and fflags follow the official FP rules; do not add implementation details not specified by the ISA.
When vm=0 uses v0.t as the execution mask, the ordinary destination vector register group must not overlap the v0 mask register.
FAQ
Do these vector floating-point instructions use vxrm?
No. VFSQRT.V uses dynamic frm when rounding is needed; FP exceptions raised by active elements accrue in fflags. vxrm controls fixed-point rounding.
How does VFSQRT.V handle NaNs, infinities, or negative inputs?
Negative inputs, NaN operands, and infinity inputs are handled by the FP rules. Results, rounding, and fflags follow the official RVV floating-point rules; this page does not simplify them into integer-style fixed results.