RISC-V VFSQRT.V Instruction Details

Instruction ManualR-type

Compute square root of each float element of vs2, writing to vd.

Instruction Syntax

vfsqrt.v vd, vs2, vm

Operand Breakdown

Destination rd: register receiving the operation result.

Source rs1: register holding the first operand.

Source rs2: register holding the second operand.

VZvfhVector OperationsFloating-Point

Related Search Terms

VFSQRT.V instruction RISC-V VFSQRT.V vfsqrt.v syntax vfsqrt.v RVV FP sqrt vector sqrt

Instruction Behavior

VFSQRT.V computes square root. The operation follows RVV floating-point rules, including NaN, rounding, and exception-flag behavior; estimate instructions provide an approximation with the precision defined by the spec. Vector FP32/FP64 operation requires the corresponding scalar F/D support; FP16 is controlled by the relevant vector half-precision extensions; do not assume the base V extension includes half-precision arithmetic.

Quick Understanding & Search Notes

VFSQRT.V is an RVV floating-point datapath instruction; reason about its result through FP semantics rather than integer bit patterns.

Exception flags and rounding behavior come from the floating-point environment.

The operation applies only to active elements within vl; inactive and tail elements follow the current vma/vta policy.

Except for dedicated mask forms, vm=0 uses v0 as the execution mask and vm=1 is unmasked.

Floating-point operations follow the vector FP rules: normal FP operations use frm rounding and set FP exception flags; fixed-point vxrm does not control them.

RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations

Common Usage Scenarios

Math Ops

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfsqrt.v v1, v2 # v1[i] = sqrt(v2[i])».

Vector Norm

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfsqrt.v v1, v2 # v1[i] = sqrt(v2[i])».

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is R-type.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Negative input → NaN (quiet). ±0→±0. +∞→+∞.

Hardware latency typically high.

Vector FP32/FP64 operations require matching scalar F/D support; FP16 operation is not implied by V alone.

FAQ

Do these floating-point instructions use vxrm?

No. Ordinary RVV floating-point operations and FP conversions use floating-point frm or an instruction-specified fixed rounding mode; vxrm is for fixed-point rounding instructions.