Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VFSQRT.V
RISC-V VFSQRT.V Instruction Details
Instruction ManualR-typeVFSQRT.V is an RVV single-width unary floating-point square-root instruction with syntax vfsqrt.v vd, vs2, vm; each active element computes vd[i] = sqrt(vs2[i]).
Instruction Syntax
vfsqrt.v vd, vs2, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VZvfhVector OperationsFloating-Point
Instruction Behavior
VFSQRT.V uses the OP-V VFUNARY1 form and has only vs2 and vm as source syntax operands; the encoded vs1 field selects the square-root operation and is not a user-written source register. Results, rounding, negative inputs, NaNs, infinities, and exception flags follow the official RVV floating-point rules; fixed-point vxrm does not control this instruction.
VFSQRT.V Decode And Execute Animation
Decode the OP-V encoding and execute the VFUNARY1 square-root operation lane by lane: each active lane computes sqrt(vs2[i]).
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Instruction input
vfsqrt.v
Execution context
frm
RNE
demo dynamic rounding modevta/vma
ta, ma
tail/inactive policyopcode
1010111
OP-V major opcodevs1
00000
VFUNARY1 square-root selectorEncoding fields
0x4c801257
31..26
25
24..20
19..15
14..12
11..7
6..0
010011
funct6
0
vm
01000
vs2
00000
vs1
001
funct3
00100
vd
1010111
OP-V
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
sqrt(1)
1
i=1active
sqrt(4)
2
i=2skip
v0.t=0, not executed
--
i=3active
sqrt(16)
4
i=4active
sqrt(25)
5
i=5active
sqrt(36)
6
i=6skip
v0.t=0, not executed
--
i=7active
sqrt(64)
8
The animation quantizes source values and results for the current SEW under the RNE demo mode: SEW=32 uses binary32 and SEW=64 uses binary64. NaN, infinity, and exception flags still follow the official RVV FP rules and are not expanded here as a full FP exception simulator.
Quick Understanding & Search Notes
VFSQRT.V is unary vector FP square root: it reads only vs2 elements and writes sqrt(vs2[i]) to vd[i]; the encoded vs1 field is an operation selector, not a syntax source operand.
In the OP-V encoding, funct6=010011 and funct3=001 are used with vs1=00000 to select the VFUNARY1 square-root operation.
The semantic operation is vd[i] = sqrt(vs2[i]) for active elements within vl.
vm=0 uses v0.t as the execution mask; vm=1 is unmasked.
Rounding, negative inputs, NaNs, infinities, and fflags follow the official RVV FP rules; vxrm is not involved.
For ordinary masked vector instructions, the destination vector register group must not overlap the v0 mask source; the animation rejects vd=v0 when vm=0.
Vector Execution Context
When reading VFSQRT.V, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Lane-wise square root
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfsqrt.v v1, v2 # v1[i] = sqrt(v2[i])».
Vector norms
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfsqrt.v v1, v2 # v1[i] = sqrt(v2[i])».
Numeric computing
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfsqrt.v v1, v2 # v1[i] = sqrt(v2[i])».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Syntax is vfsqrt.v vd, vs2, vm; do not add a vs1 or rs1 operand.
The encoded vs1=00000 is the VFUNARY1 square-root selector and does not mean v0 is read as an ordinary source vector.
Negative inputs, NaNs, infinities, rounding, and fflags follow the official FP rules; do not add implementation details not specified by the ISA.
When vm=0 uses v0.t as the execution mask, the ordinary destination vector register group must not overlap the v0 mask register.
FAQ
What does the vm operand control for VFSQRT.V?
With vm=0, only active elements selected by v0.t execute; vm=1 is unmasked. The page formula is vd[i] = sqrt(vs2[i]).
Do these vector floating-point instructions use vxrm?
No. Ordinary RVV floating-point operations use the floating-point rounding mode frm and set FP exception flags; vxrm is for fixed-point rounding instructions.
How does VFSQRT.V handle NaNs, infinities, or negative inputs?
Negative inputs, NaN operands, and infinity inputs are handled by the FP rules. Results, rounding, and fflags follow the official RVV floating-point rules; this page does not simplify them into integer-style fixed results.