Is the estimate result implementation-defined?
No. The V extension defines the 7-bit estimate and special-input handling rules.
VFREC7.V
RISC-V VFREC7.V Instruction Details
Instruction ManualOPFVVCompute approximate reciprocal (7-bit accuracy) of each float element in vs2, writing to vd.
Instruction Syntax
vfrec7.v vd, vs2, vm
Operand Breakdown
vd and vs2 are SEW-wide vector register groups; same-width source/destination overlap is allowed. An ordinary masked destination cannot overlap v0.
This unary reciprocal estimate uses a lookup table; encoded vs1=00101 is a fixed selector, not a second vector source. Ordinary results are independent of frm; tiny-input overflow depends on frm.
Assembly vm denotes optional v0.t: omission means vm=1; v0.t means vm=0, selecting active vs2 elements. One source register cannot be read as both an EEW=1 mask and SEW-wide data.
Active elements satisfy vstart≤i<vl with the mask enabled; vstart≥vl or vl=0 leaves all destination elements unchanged. Other inactive/tail destinations follow vma/vta without guaranteed zeroing.
V 1.0 applies to RV32/RV64, includes FP32/FP64, and depends on F/D; SEW=16 arithmetic requires Zvfh. Require valid vtype, supported widths, enabled VS/FS, and valid frm; invalid frm use is reserved even at vl=0. vxrm does not control these FP operations.
VVector OperationsFloating-Point
Instruction Behavior
VFREC7.V produces the specified 7-bit reciprocal estimate for each active element. Lookup and exponent adjustment determine ordinary results; dynamic frm affects the result when tiny nonzero inputs overflow. ±0 returns same-sign infinity and raises DZ; ±∞ returns same-sign zero. qNaN returns canonical NaN; sNaN also raises NV. V supports FP32/FP64; SEW=16 arithmetic requires Zvfh.
VFREC7.V Reciprocal estimate animation
Qualitative encoding demo: fixed SEW=32, LMUL=m1, VLEN=4096, vl=1, vstart=0, frm=RNE, valid vtype, and enabled VS/FS. Inputs are represented as finite nonzero FP32; lookup values and exception flags are not calculated.
Step 1/5
VFUNARY1 OP-V encoding: vs1=00101, funct3=001, vm=1.
v0-v31; vm=1
v0-v31; vm=1
finite nonzero demo value
funct6
010011
vm
1
vs2
01000
vs1
00101
funct3
001
vd
00100
opcode
1010111
Use the official manual for the complete special-value table and 7-bit lookup result; this animation validates fields, constraints, and state boundaries only.
Quick Understanding & Search Notes
Each active element uses the specified lookup rule to estimate 1/x to 7 bits.
The operation applies only to active elements within vl; inactive and tail elements follow the current vma/vta policy.
vm=0 uses v0 as the execution mask and vm=1 is unmasked.
Special-case results and exception flags should be handled using the official estimate-instruction tables.
V includes FP32/FP64 support and depends on F/D; SEW=16 arithmetic requires Zvfh.
funct6=010011, funct3=001, vs1=00101; vm controls masking.
Vector Execution Context
vd and vs2 are SEW-wide vector register groups; same-width source/destination overlap is allowed. An ordinary masked destination cannot overlap v0.
This unary reciprocal estimate uses a lookup table; encoded vs1=00101 is a fixed selector, not a second vector source. Ordinary results are independent of frm; tiny-input overflow depends on frm.
Assembly vm denotes optional v0.t: omission means vm=1; v0.t means vm=0, selecting active vs2 elements. One source register cannot be read as both an EEW=1 mask and SEW-wide data.
Active elements satisfy vstart≤i<vl with the mask enabled; vstart≥vl or vl=0 leaves all destination elements unchanged. Other inactive/tail destinations follow vma/vta without guaranteed zeroing.
V 1.0 applies to RV32/RV64, includes FP32/FP64, and depends on F/D; SEW=16 arithmetic requires Zvfh. Require valid vtype, supported widths, enabled VS/FS, and valid frm; invalid frm use is reserved even at vl=0. vxrm does not control these FP operations.
Common Usage Scenarios
Division Optimization
Assume V/VS/FS enabled, valid vtype, frm=RNE, supported e32,m1, VLMAX≥4, and x10=4; after vsetvli, vl=4 and vstart=0. Inputs are binary32; f0, when used, is validly NaN-boxed at FLEN=64. The example is unmasked: v2=[1,1,1,1] → v1=[0.99609375,0.99609375,0.99609375,0.99609375]. Tails follow ta without assumed zeroing.
Newton-Raphson
Assume V/VS/FS enabled, valid vtype, frm=RNE, supported e32,m1, VLMAX≥4, and x10=4; after vsetvli, vl=4 and vstart=0. Inputs are binary32; f0, when used, is validly NaN-boxed at FLEN=64. The example is unmasked: v2=[1,1,1,1] → v1=[0.99609375,0.99609375,0.99609375,0.99609375]. Tails follow ta without assumed zeroing.
Pre-Use Checklist
Syntax Check
- vd and vs2 are SEW-wide vector register groups; same-width source/destination overlap is allowed. An ordinary masked destination cannot overlap v0.
- This unary reciprocal estimate uses a lookup table; encoded vs1=00101 is a fixed selector, not a second vector source. Ordinary results are independent of frm; tiny-input overflow depends on frm.
Semantic Check
- Assembly vm denotes optional v0.t: omission means vm=1; v0.t means vm=0, selecting active vs2 elements. One source register cannot be read as both an EEW=1 mask and SEW-wide data.
- Active elements satisfy vstart≤i<vl with the mask enabled; vstart≥vl or vl=0 leaves all destination elements unchanged. Other inactive/tail destinations follow vma/vta without guaranteed zeroing.
- V 1.0 applies to RV32/RV64, includes FP32/FP64, and depends on F/D; SEW=16 arithmetic requires Zvfh. Require valid vtype, supported widths, enabled VS/FS, and valid frm; invalid frm use is reserved even at vl=0. vxrm does not control these FP operations.
Pitfalls / Common Confusions
This is a table-defined estimate of 1/x; later Newton-Raphson iterations can refine its accuracy.
Ordinary estimates are independent of frm, but overflow results depend on frm; all executions still require valid frm.
Masked-off elements raise no exception flags; an ordinary masked destination cannot overlap v0.