Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VFRDIV.VF
RISC-V VFRDIV.VF Instruction Details
Instruction ManualR-typeVFRDIV.VF is an RVV single-width vector-scalar reverse floating-point divide instruction with syntax vfrdiv.vf vd, vs2, rs1, vm; each active element computes vd[i] = f[rs1] / vs2[i].
Instruction Syntax
vfrdiv.vf vd, vs2, rs1, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VZvfhVector OperationsFloating-Point
Instruction Behavior
VFRDIV.VF divides the floating-point scalar f[rs1] by each active vector element vs2[i]. Its operand direction is the reverse of VFDIV.VF, so the key learning point is not to read f[rs1] / vs2[i] as vs2[i] / f[rs1]. Rounding, NaNs, infinities, divide-by-zero, and exception flags follow the official RVV floating-point rules.
VFRDIV.VF Decode And Execute Animation
Decode the OP-V encoding and execute reverse FP division lane by lane: each active lane computes f[rs1] / vs2[i].
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Instruction input
vfrdiv.vf
Execution context
frm
RNE
demo dynamic rounding modevta/vma
ta, ma
tail/inactive policyopcode
1010111
OP-V major opcodeEncoding fields
0x84855257
31..26
25
24..20
19..15
14..12
11..7
6..0
100001
funct6
0
vm
01000
vs2
01010
rs1
101
funct3
00100
vd
1010111
OP-V
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
1.5 / 1
1.5
i=1active
1.5 / 1.5
1
i=2skip
v0.t=0, not executed
--
i=3active
1.5 / 2.5
0.600000024
i=4active
1.5 / -3
-0.5
i=5active
1.5 / 3.5
0.428571433
i=6skip
v0.t=0, not executed
--
i=7active
1.5 / 4.5
0.333333343
The animation quantizes source values and results for the current SEW under the RNE demo mode: SEW=32 uses binary32 and SEW=64 uses binary64. NaN, infinity, and exception flags still follow the official RVV FP rules and are not expanded here as a full FP exception simulator.
Quick Understanding & Search Notes
VFRDIV.VF runs in the scalar-divided-by-vector direction: f[rs1] / vs2[i]. It exists to distinguish the operand direction from vfdiv.vf.
In the OP-V encoding, funct6=100001 and funct3=101 select vector-scalar reverse FP division.
The semantic operation is vd[i] = f[rs1] / vs2[i], with the scalar source from the FP register file.
vm=0 uses v0.t to control active elements; vm=1 is unmasked.
Rounding, NaNs, infinities, divide-by-zero, and fflags follow the official RVV FP rules; vxrm is not involved.
For ordinary masked vector instructions, the destination vector register group must not overlap the v0 mask source; the animation rejects vd=v0 when vm=0.
Vector Execution Context
When reading VFRDIV.VF, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vf: one vector source and one floating-point scalar source participate.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Reciprocal scaling
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfrdiv.vf v1, v2, ft0 # v1[i] = ft0 / v2[i]».
Vector normalization
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfrdiv.vf v1, v2, ft0 # v1[i] = ft0 / v2[i]».
Numeric computing
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfrdiv.vf v1, v2, ft0 # v1[i] = ft0 / v2[i]».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Operand order is f[rs1] / vs2[i]; VFDIV.VF is vs2[i] / f[rs1].
rs1 is a floating-point register source and must not be interpreted as an integer register value.
Setting f[rs1] to 1.0 expresses a lane-wise reciprocal, but NaNs, zeros, and infinities still follow the FP rules.
When vm=0 uses v0.t as the execution mask, the ordinary destination vector register group must not overlap the v0 mask register.
FAQ
What does the vm operand control for VFRDIV.VF?
With vm=0, only active elements selected by v0.t execute; vm=1 is unmasked. The page formula is vd[i] = f[rs1] / vs2[i].
Do these vector floating-point instructions use vxrm?
No. Ordinary RVV floating-point operations use the floating-point rounding mode frm and set FP exception flags; vxrm is for fixed-point rounding instructions.
How does VFRDIV.VF handle NaNs, infinities, divide-by-zero, or invalid inputs?
Divide-by-zero, 0/0, NaN operands, and infinity inputs are handled by the FP rules. Results, rounding, and fflags follow the official RVV floating-point rules; this page does not simplify them into integer-style fixed results.