What does the vm operand control for VFRDIV.VF?
With vm=0, only active elements selected by v0.t execute; vm=1 is unmasked. The page formula is vd[i] = f[rs1] / vs2[i].
VFRDIV.VF
RISC-V VFRDIV.VF Instruction Details
Instruction ManualOPFVFVFRDIV.VF is an RVV single-width vector-scalar reverse floating-point divide instruction with syntax vfrdiv.vf vd, vs2, rs1, vm; each active element computes vd[i] = f[rs1] / vs2[i].
Instruction Syntax
vfrdiv.vf vd, vs2, rs1, vm
Operand Breakdown
vd and vs2 are SEW-wide vector register groups; same-width source/destination overlap is allowed. An ordinary masked destination cannot overlap v0.
rs1 selects an FP f register; compute f[rs1]/vs2[i]. With FLEN>SEW, a valid NaN box supplies low SEW bits and an invalid box supplies canonical NaN; FLEN<SEW is reserved.
Assembly vm denotes optional v0.t: omission means vm=1; v0.t means vm=0, selecting active vs2 elements. One source register cannot be read as both an EEW=1 mask and SEW-wide data.
Active elements satisfy vstart≤i<vl with the mask enabled; vstart≥vl or vl=0 leaves all destination elements unchanged. Other inactive/tail destinations follow vma/vta without guaranteed zeroing.
V 1.0 applies to RV32/RV64, includes FP32/FP64, and depends on F/D; SEW=16 arithmetic requires Zvfh. Require valid vtype, supported widths, enabled VS/FS, and valid frm; invalid frm use is reserved even at vl=0. vxrm does not control these FP operations.
VVector OperationsFloating-Point
Instruction Behavior
VFRDIV.VF divides the floating-point scalar f[rs1] by each active vector element vs2[i]. Its operand direction is the reverse of VFDIV.VF, so the key learning point is not to read f[rs1] / vs2[i] as vs2[i] / f[rs1]. Rounding, NaNs, infinities, divide-by-zero, and exception flags follow the official RVV floating-point rules.
VFRDIV.VF Decode And Execute Animation
Decode the OP-V encoding and execute reverse FP division lane by lane: each active lane computes f[rs1] / vs2[i].
Instruction input
vfrdiv.vf
Execution context
LMULfixed register-group multiplier
VLENfixed vector-register length (bits)
VLMAXmaximum element count at m1
vstartprestart elements are outside this animation
frmfinite teaching context fixed at RNE; the architectural instruction uses dynamic frm
FP stateFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled
vta/vmatail/inactive policy
opcodeOP-V major opcode
Encoding fields
0x84855257
31..26
25
24..20
19..15
14..12
11..7
6..0
100001
funct6
0
vm
01000
vs2
01010
rs1
101
funct3
00100
vd
1010111
OP-V
Execution data path
lane 0: 1.5 / 1 -> 1.5
This lane follows the current-step highlight; the remaining lane results appear below.
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
1.5 / 1
1.5
i=1active
1.5 / 1.5
1
i=2skip
v0.t=0, not executed
--
i=3active
1.5 / 2.5
0.6000000238418579
i=4active
1.5 / -3
-0.5
i=5active
1.5 / 3.5
0.4285714328289032
i=6skip
v0.t=0, not executed
--
i=7active
1.5 / 4.5
0.3333333432674408
SEW=32 / binary32 teaching model calculates only finite, non-zero-divisor numeric paths; a zero divisor remains a legal FP condition, but this module does not disguise JavaScript Infinity/NaN as an architectural result. This view fixes frm=RNE with FS enabled; the architectural RVV instruction uses dynamic frm, FS=Off raises illegal instruction, and NaN, infinity, divide-by-zero, rounding, and fflags remain governed by the official FP rules.
Quick Understanding & Search Notes
VFRDIV.VF runs in the scalar-divided-by-vector direction: f[rs1] / vs2[i]. It exists to distinguish the operand direction from vfdiv.vf.
In the OP-V encoding, funct6=100001 and funct3=101 select vector-scalar reverse FP division.
The semantic operation is vd[i] = f[rs1] / vs2[i], with the scalar source from the FP register file.
vm=0 uses v0.t to control active elements; vm=1 is unmasked.
Rounding, NaNs, infinities, divide-by-zero, and fflags follow the official RVV FP rules; vxrm is not involved.
For ordinary masked vector instructions, the destination vector register group must not overlap the v0 mask source; the animation rejects vd=v0 when vm=0.
Vector Execution Context
vd and vs2 are SEW-wide vector register groups; same-width source/destination overlap is allowed. An ordinary masked destination cannot overlap v0.
rs1 selects an FP f register; compute f[rs1]/vs2[i]. With FLEN>SEW, a valid NaN box supplies low SEW bits and an invalid box supplies canonical NaN; FLEN<SEW is reserved.
Assembly vm denotes optional v0.t: omission means vm=1; v0.t means vm=0, selecting active vs2 elements. One source register cannot be read as both an EEW=1 mask and SEW-wide data.
Active elements satisfy vstart≤i<vl with the mask enabled; vstart≥vl or vl=0 leaves all destination elements unchanged. Other inactive/tail destinations follow vma/vta without guaranteed zeroing.
V 1.0 applies to RV32/RV64, includes FP32/FP64, and depends on F/D; SEW=16 arithmetic requires Zvfh. Require valid vtype, supported widths, enabled VS/FS, and valid frm; invalid frm use is reserved even at vl=0. vxrm does not control these FP operations.
Common Usage Scenarios
Reciprocal scaling
Assume V/VS/FS enabled, valid vtype, frm=RNE, supported e32,m1, VLMAX≥4, and x10=4; after vsetvli, vl=4 and vstart=0. Inputs are binary32; f0, when used, is validly NaN-boxed at FLEN=64. The example is unmasked: f0=8, v2=[2,4,8,16] → v1=[4,2,1,0.5]. Tails follow ta without assumed zeroing.
Vector normalization
Assume V/VS/FS enabled, valid vtype, frm=RNE, supported e32,m1, VLMAX≥4, and x10=4; after vsetvli, vl=4 and vstart=0. Inputs are binary32; f0, when used, is validly NaN-boxed at FLEN=64. The example is unmasked: f0=8, v2=[2,4,8,16] → v1=[4,2,1,0.5]. Tails follow ta without assumed zeroing.
Numeric computing
Assume V/VS/FS enabled, valid vtype, frm=RNE, supported e32,m1, VLMAX≥4, and x10=4; after vsetvli, vl=4 and vstart=0. Inputs are binary32; f0, when used, is validly NaN-boxed at FLEN=64. The example is unmasked: f0=8, v2=[2,4,8,16] → v1=[4,2,1,0.5]. Tails follow ta without assumed zeroing.
Pre-Use Checklist
Syntax Check
- vd and vs2 are SEW-wide vector register groups; same-width source/destination overlap is allowed. An ordinary masked destination cannot overlap v0.
- rs1 selects an FP f register; compute f[rs1]/vs2[i]. With FLEN>SEW, a valid NaN box supplies low SEW bits and an invalid box supplies canonical NaN; FLEN<SEW is reserved.
Semantic Check
- Assembly vm denotes optional v0.t: omission means vm=1; v0.t means vm=0, selecting active vs2 elements. One source register cannot be read as both an EEW=1 mask and SEW-wide data.
- Active elements satisfy vstart≤i<vl with the mask enabled; vstart≥vl or vl=0 leaves all destination elements unchanged. Other inactive/tail destinations follow vma/vta without guaranteed zeroing.
- V 1.0 applies to RV32/RV64, includes FP32/FP64, and depends on F/D; SEW=16 arithmetic requires Zvfh. Require valid vtype, supported widths, enabled VS/FS, and valid frm; invalid frm use is reserved even at vl=0. vxrm does not control these FP operations.
Pitfalls / Common Confusions
Operand order is f[rs1] / vs2[i]; VFDIV.VF is vs2[i] / f[rs1].
rs1 is a floating-point register source and must not be interpreted as an integer register value.
Setting f[rs1] to 1.0 expresses a lane-wise reciprocal, but NaNs, zeros, and infinities still follow the FP rules.
When vm=0 uses v0.t as the execution mask, the ordinary destination vector register group must not overlap the v0 mask register.
FAQ
Do these vector floating-point instructions use vxrm?
No. Ordinary RVV floating-point operations use the floating-point rounding mode frm and set FP exception flags; vxrm is for fixed-point rounding instructions.
How does VFRDIV.VF handle NaNs, infinities, divide-by-zero, or invalid inputs?
Divide-by-zero, 0/0, NaN operands, and infinity inputs are handled by the FP rules. Results, rounding, and fflags follow the official RVV floating-point rules; this page does not simplify them into integer-style fixed results.