Do these floating-point instructions use vxrm?
No. Ordinary RVV floating-point operations and FP conversions use floating-point frm or an instruction-specified fixed rounding mode; vxrm is for fixed-point rounding instructions.
VFRDIV.VF
RISC-V VFRDIV.VF Instruction Details
Instruction ManualR-typeDivide f[rs1] by each element of vs2: vd[i] = f[rs1] / vs2[i].
Instruction Syntax
vfrdiv.vf vd, vs2, rs1, vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
VZvfhVector OperationsFloating-Point
Instruction Behavior
VFRDIV.VF performs floating-point division. The operation follows RVV floating-point rules, including NaN, rounding, and exception-flag behavior; estimate instructions provide an approximation with the precision defined by the spec. Vector FP32/FP64 operation requires the corresponding scalar F/D support; FP16 is controlled by the relevant vector half-precision extensions; do not assume the base V extension includes half-precision arithmetic.
Quick Understanding & Search Notes
VFRDIV.VF is an RVV floating-point datapath instruction; reason about its result through FP semantics rather than integer bit patterns.
Exception flags and rounding behavior come from the floating-point environment.
The operation applies only to active elements within vl; inactive and tail elements follow the current vma/vta policy.
Except for dedicated mask forms, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
Floating-point operations follow the vector FP rules: normal FP operations use frm rounding and set FP exception flags; fixed-point vxrm does not control them.
Common Usage Scenarios
Reciprocal
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfrdiv.vf v1, v2, ft0 # v1[i] = ft0 / v2[i]».
Normalization
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfrdiv.vf v1, v2, ft0 # v1[i] = ft0 / v2[i]».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Operand order: vd = f[rs1] / vs2 (NOT vs2 / f[rs1]!). vfdiv.vf is conventional division.
With f[rs1]=1.0, computes reciprocals of entire vector in one instruction.
Vector FP32/FP64 operations require matching scalar F/D support; FP16 operation is not implied by V alone.