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VFDIV.VV

RISC-V VFDIV.VV Instruction Details

Instruction ManualR-type

VFDIV.VV is an RVV single-width floating-point divide instruction with syntax vfdiv.vv vd, vs2, vs1, vm; each active element computes vd[i] = vs2[i] / vs1[i].

Instruction Syntax

vfdiv.vv vd, vs2, vs1, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VZvfhVector OperationsFloating-Point
Related Search Terms
VFDIV.VV instructionRISC-V VFDIV.VVvfdiv.vv syntaxvfdiv.vv encodingRVV FP dividevfdiv.vv mask executionvfdiv.vv frm rounding

Instruction Behavior

VFDIV.VV performs same-lane floating-point division on active elements within vl. The second source is vs1[i], not a scalar register; with vm=0, v0.t controls which elements execute, and vm=1 is unmasked. Rounding mode, NaNs, infinities, divide-by-zero, and exception flags follow the official RVV floating-point rules; fixed-point vxrm does not control this instruction.

VFDIV.VV Decode And Execute Animation

Decode the OP-V encoding and execute lane-wise FP division with the second source from same-lane vs1.

Step 1 / 15
Read OP-V encoding fields

V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.

Instruction input
vfdiv.vv
Execution context
frm
RNE
demo dynamic rounding mode
vta/vma
ta, ma
tail/inactive policy
opcode
1010111
OP-V major opcode
Encoding fields
0x80861257
31..26
25
24..20
19..15
14..12
11..7
6..0
100000
funct6
0
vm
01000
vs2
01100
vs1
001
funct3
00100
vd
1010111
OP-V
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
1 / 0.5
2
i=1active
1.5 / 1
1.5
i=2skip
v0.t=0, not executed
--
i=3active
2.5 / 2
1.25
i=4active
-3 / 2.5
-1.20000005
i=5active
3.5 / 3
1.16666663
i=6skip
v0.t=0, not executed
--
i=7active
4.5 / 4
1.125
The animation quantizes source values and results for the current SEW under the RNE demo mode: SEW=32 uses binary32 and SEW=64 uses binary64. NaN, infinity, and exception flags still follow the official RVV FP rules and are not expanded here as a full FP exception simulator.

Quick Understanding & Search Notes

VFDIV.VV divides same-lane vs2[i] by vs1[i] and writes vd[i]; it is ordinary FP division, not a reciprocal estimate or integer division.

In the OP-V encoding, funct6=100000 and funct3=001 select vector-vector FP division.
The semantic operation is vd[i] = vs2[i] / vs1[i] for active elements within vl.
vm=0 uses v0.t as the execution mask; vm=1 is unmasked.
Rounding, NaNs, infinities, divide-by-zero, and fflags follow the official RVV FP rules; vxrm is not involved.
For ordinary masked vector instructions, the destination vector register group must not overlap the v0 mask source; the animation rejects vd=v0 when vm=0.
RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations

Vector Execution Context

When reading VFDIV.VV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vv: two vector sources participate element by element.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Lane-wise FP division

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfdiv.vv v1, v2, v3 # v1[i] = v2[i] / v3[i]».

Vector normalization

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfdiv.vv v1, v2, v3 # v1[i] = v2[i] / v3[i]».

Numeric computing

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfdiv.vv v1, v2, v3 # v1[i] = v2[i] / v3[i]».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Operand order is vs2[i] / vs1[i]; do not swap vs1 and vs2.
Floating-point divide-by-zero, 0/0, NaNs, and signs follow the official FP rules and are not integer division behavior.
Only active elements selected by v0.t execute; masked-off elements do not produce the divide result shown on this page.
When vm=0 uses v0.t as the execution mask, the ordinary destination vector register group must not overlap the v0 mask register.

FAQ

What does the vm operand control for VFDIV.VV?

With vm=0, only active elements selected by v0.t execute; vm=1 is unmasked. The page formula is vd[i] = vs2[i] / vs1[i].

Do these vector floating-point instructions use vxrm?

No. Ordinary RVV floating-point operations use the floating-point rounding mode frm and set FP exception flags; vxrm is for fixed-point rounding instructions.

How does VFDIV.VV handle NaNs, infinities, divide-by-zero, or invalid inputs?

Divide-by-zero, 0/0, NaN operands, and infinity inputs are handled by the FP rules. Results, rounding, and fflags follow the official RVV floating-point rules; this page does not simplify them into integer-style fixed results.