What does the vm operand control for VFDIV.VV?
With vm=0, only active elements selected by v0.t execute; vm=1 is unmasked. The page formula is vd[i] = vs2[i] / vs1[i].
VFDIV.VV
RISC-V VFDIV.VV Instruction Details
Instruction ManualV-typeVFDIV.VV is an RVV single-width floating-point divide instruction with syntax vfdiv.vv vd, vs2, vs1, vm; each active element computes vd[i] = vs2[i] / vs1[i].
Instruction Syntax
vfdiv.vv vd, vs2, vs1[, v0.t]
Operand Breakdown
vd and vs2 are SEW-wide vector groups; same-EEW source/destination overlap is allowed. The assembly vm operand is optional v0.t; omitting it means vm=1.
vs1 is the same-SEW vector divisor and vs2 the dividend; equal source registers read equal initial values. Compute vs2[i]/vs1[i].
Require V, enabled VS/FS, and supported vtype. V supports binary32/64; these instructions at SEW=16 require Zvfh. VS/FS=Off raises illegal instruction; with H and virtualization V=1, vsstatus.VS/FS must also be enabled.
Active elements satisfy vstart≤i<vl and (vm=1 or v0[i]=1). Prestart elements are unchanged; inactive/tail elements follow vma/vta. VL=0 or vstart≥vl leaves the entire destination unchanged; successful completion resets vstart=0.
Masked vd cannot overlap v0; v0 cannot supply both an EEW=1 mask and SEW data source. Invalid frm use is reserved even at VL=0 or vstart≥vl; an illegal-instruction exception is not guaranteed. Only active-element exceptions accrue in fflags; fixed-point vxrm is not used.
The FP quotient rounds using dynamic frm. The animation fixes RNE and shows only finite results and non-zero divisors; legal zero divisors, NaNs, infinities, overflow, and fflags are outside this model.
VVector OperationsFloating-Point
Instruction Behavior
VFDIV.VV performs same-lane floating-point division on active elements within vl. The second source is vs1[i], not a scalar register; with vm=0, v0.t controls which elements execute, and vm=1 is unmasked. Rounding mode, NaNs, infinities, divide-by-zero, and exception flags follow the official RVV floating-point rules; fixed-point vxrm does not control this instruction.
VFDIV.VV Decode And Execute Animation
Decode the OP-V encoding and execute lane-wise FP division with the second source from same-lane vs1.
Instruction input
vfdiv.vv
Execution context
LMULfixed register-group multiplier
VLENfixed vector-register length (bits)
VLMAXmaximum element count at m1
vstartprestart elements are outside this animation
frmfinite teaching context fixed at RNE; the architectural instruction uses dynamic frm
FP stateFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled
vta/vmatail/inactive policy
opcodeOP-V major opcode
Encoding fields
0x80861257
31..26
25
24..20
19..15
14..12
11..7
6..0
100000
funct6
0
vm
01000
vs2
01100
vs1
001
funct3
00100
vd
1010111
OP-V
Execution data path
lane 0: 1 / 0.5 -> 2
This lane follows the current-step highlight; the remaining lane results appear below.
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
1 / 0.5
2
i=1active
1.5 / 1
1.5
i=2skip
v0.t=0, not executed
--
i=3active
2.5 / 2
1.25
i=4active
-3 / 2.5
-1.2000000476837158
i=5active
3.5 / 3
1.1666666269302368
i=6skip
v0.t=0, not executed
--
i=7active
4.5 / 4
1.125
SEW=32 / binary32 finite teaching model represents inputs before rounding the quotient under RNE; VF scalars are read at FLEN=64, with valid NaN-boxing assumed for SEW=32. Only finite results and non-zero divisors are shown; overflow, NaNs, infinities, zero divisors, and fflags are outside this model. These FP conditions do not imply an illegal encoding; the real instruction uses dynamic frm and the official exception rules.
The teaching context fixes VLEN=4096, LMUL=m1, vstart=0, enabled VS/FS, and supported SEW. FP inputs are first represented as binary32/64. VL=0 updates no destination elements; same-width source/destination overlap is allowed. Inactive and tail values follow ma/ta without definite displayed values.
Quick Understanding & Search Notes
VFDIV.VV divides same-lane vs2[i] by vs1[i] and writes vd[i]; it is ordinary FP division, not a reciprocal estimate or integer division.
In the OP-V encoding, funct6=100000 and funct3=001 select vector-vector FP division.
The semantic operation is vd[i] = vs2[i] / vs1[i] for active elements within vl.
vm=0 uses v0.t as the execution mask; vm=1 is unmasked.
Rounding, NaNs, infinities, divide-by-zero, and fflags follow the official RVV FP rules; vxrm is not involved.
For ordinary masked vector instructions, the destination vector register group must not overlap the v0 mask source; the animation rejects vd=v0 when vm=0.
Vector Execution Context
vd and vs2 are SEW-wide vector groups; same-EEW source/destination overlap is allowed. The assembly vm operand is optional v0.t; omitting it means vm=1.
vs1 is the same-SEW vector divisor and vs2 the dividend; equal source registers read equal initial values. Compute vs2[i]/vs1[i].
Require V, enabled VS/FS, and supported vtype. V supports binary32/64; these instructions at SEW=16 require Zvfh. VS/FS=Off raises illegal instruction; with H and virtualization V=1, vsstatus.VS/FS must also be enabled.
Active elements satisfy vstart≤i<vl and (vm=1 or v0[i]=1). Prestart elements are unchanged; inactive/tail elements follow vma/vta. VL=0 or vstart≥vl leaves the entire destination unchanged; successful completion resets vstart=0.
Masked vd cannot overlap v0; v0 cannot supply both an EEW=1 mask and SEW data source. Invalid frm use is reserved even at VL=0 or vstart≥vl; an illegal-instruction exception is not guaranteed. Only active-element exceptions accrue in fflags; fixed-point vxrm is not used.
The FP quotient rounds using dynamic frm. The animation fixes RNE and shows only finite results and non-zero divisors; legal zero divisors, NaNs, infinities, overflow, and fflags are outside this model.
Common Usage Scenarios
Lane-wise FP division
Assume V/VS/FS enabled, frm=RNE, vstart=0, supported e32,m1, VLMAX≥4 and a0=4. The example is unmasked, so all four body elements execute. Initial values and results: v2=[1,2,-3,4.5], v3=[0.5,-1,3,1.5] → v1=[2,-2,-1,3]. VF scalars are assumed validly NaN-boxed; tails follow ta without assumed zeroing.
Vector normalization
Assume V/VS/FS enabled, frm=RNE, vstart=0, supported e32,m1, VLMAX≥4 and a0=4. The example is unmasked, so all four body elements execute. Initial values and results: v2=[1,2,-3,4.5], v3=[0.5,-1,3,1.5] → v1=[2,-2,-1,3]. VF scalars are assumed validly NaN-boxed; tails follow ta without assumed zeroing.
Numeric computing
Assume V/VS/FS enabled, frm=RNE, vstart=0, supported e32,m1, VLMAX≥4 and a0=4. The example is unmasked, so all four body elements execute. Initial values and results: v2=[1,2,-3,4.5], v3=[0.5,-1,3,1.5] → v1=[2,-2,-1,3]. VF scalars are assumed validly NaN-boxed; tails follow ta without assumed zeroing.
Pre-Use Checklist
Syntax Check
- vd and vs2 are SEW-wide vector groups; same-EEW source/destination overlap is allowed. The assembly vm operand is optional v0.t; omitting it means vm=1.
- vs1 is the same-SEW vector divisor and vs2 the dividend; equal source registers read equal initial values. Compute vs2[i]/vs1[i].
Semantic Check
- Require V, enabled VS/FS, and supported vtype. V supports binary32/64; these instructions at SEW=16 require Zvfh. VS/FS=Off raises illegal instruction; with H and virtualization V=1, vsstatus.VS/FS must also be enabled.
- Active elements satisfy vstart≤i<vl and (vm=1 or v0[i]=1). Prestart elements are unchanged; inactive/tail elements follow vma/vta. VL=0 or vstart≥vl leaves the entire destination unchanged; successful completion resets vstart=0.
- Masked vd cannot overlap v0; v0 cannot supply both an EEW=1 mask and SEW data source. Invalid frm use is reserved even at VL=0 or vstart≥vl; an illegal-instruction exception is not guaranteed. Only active-element exceptions accrue in fflags; fixed-point vxrm is not used.
- The FP quotient rounds using dynamic frm. The animation fixes RNE and shows only finite results and non-zero divisors; legal zero divisors, NaNs, infinities, overflow, and fflags are outside this model.
Pitfalls / Common Confusions
Operand order is vs2[i] / vs1[i]; do not swap vs1 and vs2.
Floating-point divide-by-zero, 0/0, NaNs, and signs follow the official FP rules and are not integer division behavior.
With vm=0, only active elements selected by v0.t execute; vm=1 is unmasked. Masked-off elements do not produce division results.
When vm=0 uses v0.t as the execution mask, the ordinary destination vector register group must not overlap the v0 mask register.
FAQ
Do these vector floating-point instructions use vxrm?
No. Ordinary RVV floating-point operations use the floating-point rounding mode frm and set FP exception flags; vxrm is for fixed-point rounding instructions.
How does VFDIV.VV handle NaNs, infinities, divide-by-zero, or invalid inputs?
Divide-by-zero, 0/0, NaN operands, and infinity inputs are handled by the FP rules. Results, rounding, and fflags follow the official RVV floating-point rules; this page does not simplify them into integer-style fixed results.