Does VFMUL.VV use vxrm?
No. Ordinary RVV FP arithmetic uses the floating-point rounding environment frm or the instruction-defined FP rounding rule; vxrm is for fixed-point rounding instructions.
VFMUL.VV
RISC-V VFMUL.VV Instruction Details
Instruction ManualV-type (OP-V / OPFVV)VFMUL.VV performs vector-vector FP multiply on active elements within VL: vd[i] = vs2[i] * vs1[i].
Instruction Syntax
vfmul.vv vd, vs2, vs1, vm
Operand Breakdown
Syntax is vd, vs2, vs1, vm. Two SEW-wide vector sources multiply element by element, without a separate old-vd input. Same-width source/destination overlap is legal; equal sources require equal initial values.
funct6=100100, funct3=001, opcode=1010111. V supports FP32/64; SEW=16 multiplication requires Zvfh.
vm is optional v0.t; omission means vm=1. Only elements with vstart≤i<vl and an enabled mask compute. Masked vd cannot overlap v0, and a data source cannot also read the v0 mask with another EEW.
At vl=0 or vstart≥vl no destination elements, including tails, change; prestart is unchanged. Other inactive/tail values follow vma/vta, subject to the different-EEW overlap exception above. Successful execution resets vstart=0.
Products round using dynamic frm; only active-element exceptions accrue in fflags. The animation supports finite binary32/64 under fixed RNE without NaNs, infinities, overflow, or full fflags.
Require valid vtype, supported FP widths and matching scalar FP extensions, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0 or for operations that do not round; vxrm does not control FP operations.
VVector Multiply
Instruction Behavior
VFMUL.VV is an RVV single-width floating-point multiplication instruction with syntax vfmul.vv vd, vs2, vs1, vm. Each active element uses the current SEW FP format to execute vd[i] = vs2[i] * vs1[i]; this is ordinary lane-wise multiplication and has no separate old-vd input operand; if vd aliases a source, that source still supplies its old value. With vm=0, v0.t controls active elements; with vm=1, execution is unmasked. Rounding mode and exception flags follow the official RVV floating-point rules, and fixed-point vxrm does not control these instructions. At SEW=16, this instruction is defined only when Zvfh is implemented.
VFMUL.VV Decode And Execute Animation
Decode the OP-V encoding and execute lane-wise FP multiplication with the second source from same-lane vs1.
Instruction input
vfmul.vv
Execution context
LMULfixed register-group multiplier
VLENfixed vector-register length (bits)
VLMAXmaximum element count at m1
vstartprestart elements are outside this animation
frmfinite teaching context fixed at RNE; the architectural instruction uses dynamic frm
FP stateFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled
vta/vmatail/inactive policy
opcodeOP-V major opcode
Encoding fields
0x90861257
31..26
25
24..20
19..15
14..12
11..7
6..0
100100
funct6
0
vm
01000
vs2
01100
vs1
001
funct3
00100
vd
1010111
OP-V
Execution data path
lane 0: 1 * 0.5 -> 0.5
This lane follows the current-step highlight; the remaining lane results appear below.
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
1 * 0.5
0.5
i=1active
1.5 * 1
1.5
i=2skip
v0.t=0, not executed
--
i=3active
2.5 * 2
5
i=4active
-3 * 2.5
-7.5
i=5active
3.5 * 3
10.5
i=6skip
v0.t=0, not executed
--
i=7active
4.5 * 4
18
The finite vector-vector multiplication model represents binary32/64 inputs before rounding the product under RNE. NaNs, infinities, overflow, and fflags are outside the model; the real instruction uses dynamic frm and the official exception rules.
The teaching context fixes VLEN=4096, LMUL=m1, vstart=0, enabled VS/FS, frm=RNE, and supported FP widths. VL=0 updates no destination elements, including tails. Both sources here are vectors; no FP scalar is read. Equal sources require equal initial bits. Same-width destination/source overlap is legal. Inactive and tail elements follow ma/ta without definite displayed values.
Quick Understanding & Search Notes
VFMUL.VV is best understood through OP-V encoding, the same-lane vs1 element, v0.t masking, and per-element vd[i] = vs2[i] * vs1[i].
funct6=100100, funct3=001, and opcode=1010111 identify this OP-V FP arithmetic form.
In vfmul.vv vd, vs2, vs1, vm, vm controls execution masking; vm=0 uses v0.t and vm=1 is unmasked.
For `.vv` forms, each lane reads vs2[i] and vs1[i]; this is not a reduction or cross-lane operation.
Results, NaNs, infinities, rounding, and fflags follow the official vector floating-point rules.
Vector Execution Context
Syntax is vd, vs2, vs1, vm. Two SEW-wide vector sources multiply element by element, without a separate old-vd input. Same-width source/destination overlap is legal; equal sources require equal initial values.
funct6=100100, funct3=001, opcode=1010111. V supports FP32/64; SEW=16 multiplication requires Zvfh.
vm is optional v0.t; omission means vm=1. Only elements with vstart≤i<vl and an enabled mask compute. Masked vd cannot overlap v0, and a data source cannot also read the v0 mask with another EEW.
At vl=0 or vstart≥vl no destination elements, including tails, change; prestart is unchanged. Other inactive/tail values follow vma/vta, subject to the different-EEW overlap exception above. Successful execution resets vstart=0.
Products round using dynamic frm; only active-element exceptions accrue in fflags. The animation supports finite binary32/64 under fixed RNE without NaNs, infinities, overflow, or full fflags.
Require valid vtype, supported FP widths and matching scalar FP extensions, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0 or for operations that do not round; vxrm does not control FP operations.
Common Usage Scenarios
Vector FP Multiply
Assume V/VS/FS enabled, valid vtype, frm=RNE, supported e32,m1 and required FP formats, FLEN=64, VLMAX≥4, a0=4, and vstart=0 after vsetvli. Both vector sources hold binary32 values. The example is unmasked: v2=[2,4,-2,0], v3=[3,-1,2,5] → v1=[6,-4,-4,+0]. Elements after vl are tail; ta does not guarantee zeros.
Element-wise Multiply
Assume V/VS/FS enabled, valid vtype, frm=RNE, supported e32,m1 and required FP formats, FLEN=64, VLMAX≥4, a0=4, and vstart=0 after vsetvli. Both vector sources hold binary32 values. The example is unmasked: v2=[2,4,-2,0], v3=[3,-1,2,5] → v1=[6,-4,-4,+0]. Elements after vl are tail; ta does not guarantee zeros.
Pre-Use Checklist
Syntax Check
- Syntax is vd, vs2, vs1, vm. Two SEW-wide vector sources multiply element by element, without a separate old-vd input. Same-width source/destination overlap is legal; equal sources require equal initial values.
- funct6=100100, funct3=001, opcode=1010111. V supports FP32/64; SEW=16 multiplication requires Zvfh.
Semantic Check
- vm is optional v0.t; omission means vm=1. Only elements with vstart≤i<vl and an enabled mask compute. Masked vd cannot overlap v0, and a data source cannot also read the v0 mask with another EEW.
- At vl=0 or vstart≥vl no destination elements, including tails, change; prestart is unchanged. Other inactive/tail values follow vma/vta, subject to the different-EEW overlap exception above. Successful execution resets vstart=0.
- Products round using dynamic frm; only active-element exceptions accrue in fflags. The animation supports finite binary32/64 under fixed RNE without NaNs, infinities, overflow, or full fflags.
- Require valid vtype, supported FP widths and matching scalar FP extensions, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0 or for operations that do not round; vxrm does not control FP operations.
Pitfalls / Common Confusions
This is ordinary lane-wise multiplication; it has no separate old-vd input operand; if vd aliases a source, that source still supplies its old value.
Only elements within VL whose execution mask is true execute; inactive and tail elements follow the current vma/vta policy.
Ordinary RVV FP arithmetic uses the floating-point rounding environment frm / dynamic rounding semantics, not fixed-point vxrm.
Do not treat finite demo values in the browser animation as a full IEEE 754 exception simulator; NaN, infinity, and fflags follow the official manual.
FAQ
What does the vm operand mean for VFMUL.VV?
vm=0 uses v0.t as the execution mask; vm=1 is unmasked. It is not an ordinary data source register.