Do these floating-point instructions use vxrm?
No. Ordinary RVV floating-point operations and FP conversions use floating-point frm or an instruction-specified fixed rounding mode; vxrm is for fixed-point rounding instructions.
VFMUL.VF
RISC-V VFMUL.VF Instruction Details
Instruction ManualR-typeMultiply each float element of vs2 by f register rs1, writing to vd.
Instruction Syntax
vfmul.vf vd, vs2, rs1, vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
VZvfhVector Multiply-AddFloating-Point
Instruction Behavior
VFMUL.VF performs vector floating-point multiply. Results follow IEEE 754/RVV floating-point rules; source and destination elements use the current SEW. Vector FP32/FP64 operation requires the corresponding scalar F/D support; FP16 is controlled by the relevant vector half-precision extensions; do not assume the base V extension includes half-precision arithmetic.
Quick Understanding & Search Notes
The key property of VFMUL.VF is fused semantics: the product is not rounded before the add/subtract, so it is not equivalent to a separately rounded MUL followed by ADD.
Single-width forms use the current SEW for FP elements.
vd can be a read/write operand, so register allocation must not treat it as a pure destination.
The operation applies only to active elements within vl; inactive and tail elements follow the current vma/vta policy.
Except for dedicated mask forms, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
Floating-point operations follow the vector FP rules: normal FP operations use frm rounding and set FP exception flags; fixed-point vxrm does not control them.
Common Usage Scenarios
Scaling
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfmul.vf v1, v2, ft0 # v1[i] = v2[i] * ft0».
Gain Adjustment
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfmul.vf v1, v2, ft0 # v1[i] = v2[i] * ft0».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Scalar from f register — not x register (unlike integer vadd.vx).
vfwmul.vf for widening multiply (output 2×SEW).
Vector FP32/FP64 operations require matching scalar F/D support; FP16 operation is not implied by V alone.