How is it different from VFMV.S.F?
VFMV.S.F writes only element 0; VFMV.V.F broadcasts the scalar to active elements.
VFMV.V.F
RISC-V VFMV.V.F Instruction Details
Instruction ManualV-type (OP-V / OPFVF)Copy scalar f register rs1 to all active elements of vd; tail follows policy.
Instruction Syntax
vfmv.v.f vd, rs1
Operand Breakdown
Syntax is vd, rs1. vd selects a vector register group and rs1 selects FP f0–f31 (or an ABI name). The scalar is broadcast to active body elements.
funct6=010111, funct3=101, vs2=v0, vm=1; other vs2 values are reserved. It shares encoding with vm=0 VFMERGE.VFM, but has no execution mask.
Only vstart≤i<vl receive the scalar; prestart is unchanged and tails follow vta. At vstart≥vl (including vl=0) no destination elements, including tails, change; successful execution resets vstart=0.
At FLEN>SEW the scalar must be validly NaN-boxed or is read as canonical NaN; FLEN<SEW is reserved. V supports FP32/64; SEW=16 broadcast requires Zvfh. The animation fixes SEW=FLEN=64, VLEN=4096, LMUL=m1, and support for the selected vstart.
Require valid vtype, supported FP widths and matching scalar FP extensions, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0 or for operations that do not round; vxrm does not control FP operations.
VVector OperationsRegister Move
Related Search Terms
Instruction Behavior
VFMV.V.F broadcasts floating-point scalar f[rs1] to all active elements of the vd vector register group. It is fixed at vm=1 with vs2=v0; other vs2 values are reserved. It shares an encoding with VFMERGE.VFM, whose vm is fixed at 0. At SEW=16, this instruction is defined only when Zvfh is implemented.
VFMV.V.F Decode And Execute Animation
The teaching context fixes SEW=FLEN=64, VLEN=4096, valid vtype, frm=RNE, enabled VS/FS, and support for the selected vstart. Inputs are represented as finite binary64 before copying their bits. The model shows movement, encoding, and vstart/vl conditions, without simulating NaNs, exception flags, or microarchitecture.
Instruction input
Execution context
FP stateFS enabledFS=Off raises illegal instruction
Encoding fields
funct6=010111 | vm=1 | vs2=00000 (v0) | vs1/rs1=ft0 | funct3=101 | vd/rd=00100 | opcode=1010111
hex: 0x5e005257
VFMV.V.F shares an encoding with VFMERGE.VFM; only vm=1 with vs2=v0 is this instruction.
Architectural data path
f[ft0] -> vd[0]..vd[3]
Step 1 / 4
VFMV.V.F uses OP-V; vm is fixed to 1, vs2 is fixed to v0 and other vs2 values are reserved.
Quick Understanding & Search Notes
VFMV.V.F is FP scalar broadcast, writing f[rs1] to the current active elements.
The scalar value is written only to active elements within vl; inactive and tail elements follow the current policies.
VFMV.V.F is encoded as the unmasked scalar splat form, has no execution-mask operand, and does not use v0 for selection.
Vector Execution Context
Syntax is vd, rs1. vd selects a vector register group and rs1 selects FP f0–f31 (or an ABI name). The scalar is broadcast to active body elements.
funct6=010111, funct3=101, vs2=v0, vm=1; other vs2 values are reserved. It shares encoding with vm=0 VFMERGE.VFM, but has no execution mask.
Only vstart≤i<vl receive the scalar; prestart is unchanged and tails follow vta. At vstart≥vl (including vl=0) no destination elements, including tails, change; successful execution resets vstart=0.
At FLEN>SEW the scalar must be validly NaN-boxed or is read as canonical NaN; FLEN<SEW is reserved. V supports FP32/64; SEW=16 broadcast requires Zvfh. The animation fixes SEW=FLEN=64, VLEN=4096, LMUL=m1, and support for the selected vstart.
Require valid vtype, supported FP widths and matching scalar FP extensions, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0 or for operations that do not round; vxrm does not control FP operations.
Common Usage Scenarios
Vector Init
Assume V/VS/FS enabled, valid vtype, frm=RNE, supported e32,m1 and required FP formats, FLEN=64, VLMAX≥4, a0=4, and vstart=0 after vsetvli. ft0 is validly NaN-boxed at FLEN=64. The example is unmasked: ft0=1.5 → v1[0..3]=[1.5,1.5,1.5,1.5]. Elements after vl are tail; ta does not guarantee zeros.
Constant Broadcast
Assume V/VS/FS enabled, valid vtype, frm=RNE, supported e32,m1 and required FP formats, FLEN=64, VLMAX≥4, a0=4, and vstart=0 after vsetvli. ft0 is validly NaN-boxed at FLEN=64. The example is unmasked: ft0=1.5 → v1[0..3]=[1.5,1.5,1.5,1.5]. Elements after vl are tail; ta does not guarantee zeros.
Pre-Use Checklist
Syntax Check
- Syntax is vd, rs1. vd selects a vector register group and rs1 selects FP f0–f31 (or an ABI name). The scalar is broadcast to active body elements.
- funct6=010111, funct3=101, vs2=v0, vm=1; other vs2 values are reserved. It shares encoding with vm=0 VFMERGE.VFM, but has no execution mask.
Semantic Check
- Only vstart≤i<vl receive the scalar; prestart is unchanged and tails follow vta. At vstart≥vl (including vl=0) no destination elements, including tails, change; successful execution resets vstart=0.
- At FLEN>SEW the scalar must be validly NaN-boxed or is read as canonical NaN; FLEN<SEW is reserved. V supports FP32/64; SEW=16 broadcast requires Zvfh. The animation fixes SEW=FLEN=64, VLEN=4096, LMUL=m1, and support for the selected vstart.
- Require valid vtype, supported FP widths and matching scalar FP extensions, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0 or for operations that do not round; vxrm does not control FP operations.
Pitfalls / Common Confusions
This broadcasts to active elements; it is not an element-0-only move.
It is the fixed vm=1, vs2=v0 unmasked encoding; other vs2 values are reserved.