Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VFMV.F.S
RISC-V VFMV.F.S Instruction Details
Instruction ManualV-type (OP-V / OPFVV)Copy element 0 (float) of vs2 to scalar f register rd.
Instruction Syntax
vfmv.f.s rd, vs2
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector OperationsRegister Move
Related Search Terms
Instruction Behavior
VFMV.F.S copies the SEW-wide element 0 of vector source vs2 to floating-point scalar register rd. It ignores LMUL and vector register groups, and executes even when vstart >= vl or vl=0. The masked vm=0 encodings are reserved, so this instruction executes with vm=1. At SEW=16, this instruction is defined only when Zvfh is implemented.
VFMV.F.S Decode And Execute Animation
This model shows only architecturally visible register movement, fixed encoding, and vstart/vl conditions; it does not simulate NaNs, exception flags, or microarchitecture.
Instruction input
Execution context
FP stateFS enabledFS=Off raises illegal instruction
Encoding fields
funct6=010000 | vm=1 | vs2=v8 | vs1/rs1=00000 | funct3=001 | opcode=1010111
hex: 0x42801057
The vm=0 encodings of both element-0 FP scalar moves are reserved.
Architectural data path
v8[0] -> f[ft0]
Step 1 / 4
VFMV.F.S uses OP-V; vm is fixed to 1, and the masked vm=0 encodings are reserved.
Quick Understanding & Search Notes
VFMV.F.S moves vector element 0 to a floating-point scalar register.
Do not treat it as element-wise vector arithmetic controlled by the normal execution mask.
Vector Execution Context
When reading VFMV.F.S, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Reduction Result
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfmv.f.s ft0, v1 # ft0 = v1[0]».
Scalar-Vector Interface
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfmv.f.s ft0, v1 # ft0 = v1[0]».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is V-type (OP-V / OPFVV).
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Only element 0 is copied, not the whole vector; the move still executes when vstart >= vl or vl=0.
The destination is a floating-point scalar register; the integer version is VMV.X.S.
FAQ
Does it copy the whole vector?
No. It reads only element 0 of vs2 and writes floating-point scalar rd.