Does it copy the whole vector?
No. It reads only element 0 of vs2 and writes floating-point scalar rd.
VFMV.F.S
RISC-V VFMV.F.S Instruction Details
Instruction ManualV-type (OP-V / OPFVV)Copy element 0 (float) of vs2 to scalar f register rd.
Instruction Syntax
vfmv.f.s rd, vs2
Operand Breakdown
Syntax is rd, vs2. rd is FP f0–f31 (or an ABI name), and vs2 is one vector register; only the SEW bits of vs2[0] are copied.
funct6=010000, funct3=001, vs1=00000, vm=1; vm=0 is reserved and there is no execution-mask operand.
LMUL and vector register groups are ignored; the FP scalar is written even at vstart≥vl or vl=0. Writing a result narrower than FLEN sets all upper bits to 1 for a valid NaN box.
V supports FP32/FP64 and depends on F/D; this move at SEW=16 requires Zvfh. The animation shows finite-value bit copies at SEW=FLEN=64 without FP flags.
Require valid vtype, supported FP widths and matching scalar FP extensions, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0 or for operations that do not round; vxrm does not control FP operations.
VVector OperationsRegister Move
Related Search Terms
Instruction Behavior
VFMV.F.S copies the SEW-wide element 0 of vector source vs2 to floating-point scalar register rd. It ignores LMUL and vector register groups, and executes even when vstart >= vl or vl=0. The masked vm=0 encodings are reserved, so this instruction executes with vm=1. At SEW=16, this instruction is defined only when Zvfh is implemented.
VFMV.F.S Decode And Execute Animation
The teaching context fixes SEW=FLEN=64, VLEN=4096, valid vtype, frm=RNE, enabled VS/FS, and support for the selected vstart. Inputs are represented as finite binary64 before copying their bits. The model shows movement, encoding, and vstart/vl conditions, without simulating NaNs, exception flags, or microarchitecture.
Instruction input
Execution context
FP stateFS enabledFS=Off raises illegal instruction
Encoding fields
funct6=010000 | vm=1 | vs2=v8 | vs1/rs1=00000 | funct3=001 | vd/rd=00000 | opcode=1010111
hex: 0x42801057
The vm=0 encodings of both element-0 FP scalar moves are reserved.
Architectural data path
v8[0] -> f[ft0]
Step 1 / 4
VFMV.F.S uses OP-V; vm is fixed to 1, and the masked vm=0 encodings are reserved.
Quick Understanding & Search Notes
VFMV.F.S moves vector element 0 to a floating-point scalar register.
Do not treat it as element-wise vector arithmetic controlled by the normal execution mask.
Vector Execution Context
Syntax is rd, vs2. rd is FP f0–f31 (or an ABI name), and vs2 is one vector register; only the SEW bits of vs2[0] are copied.
funct6=010000, funct3=001, vs1=00000, vm=1; vm=0 is reserved and there is no execution-mask operand.
LMUL and vector register groups are ignored; the FP scalar is written even at vstart≥vl or vl=0. Writing a result narrower than FLEN sets all upper bits to 1 for a valid NaN box.
V supports FP32/FP64 and depends on F/D; this move at SEW=16 requires Zvfh. The animation shows finite-value bit copies at SEW=FLEN=64 without FP flags.
Require valid vtype, supported FP widths and matching scalar FP extensions, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0 or for operations that do not round; vxrm does not control FP operations.
Common Usage Scenarios
Reduction Result
Assume V/VS/FS enabled, valid vtype, frm=RNE, supported e32,m1 and required FP formats, FLEN=64, VLMAX≥4, a0=4, and vstart=0 after vsetvli. Writing ft0 creates a valid binary32 NaN box. The example is unmasked: v1[0]=2.25 → ft0=2.25. This form writes only the FP scalar, without a vector destination update.
Scalar-Vector Interface
Assume V/VS/FS enabled, valid vtype, frm=RNE, supported e32,m1 and required FP formats, FLEN=64, VLMAX≥4, a0=4, and vstart=0 after vsetvli. Writing ft0 creates a valid binary32 NaN box. The example is unmasked: v1[0]=2.25 → ft0=2.25. This form writes only the FP scalar, without a vector destination update.
Pre-Use Checklist
Syntax Check
- Syntax is rd, vs2. rd is FP f0–f31 (or an ABI name), and vs2 is one vector register; only the SEW bits of vs2[0] are copied.
- funct6=010000, funct3=001, vs1=00000, vm=1; vm=0 is reserved and there is no execution-mask operand.
Semantic Check
- LMUL and vector register groups are ignored; the FP scalar is written even at vstart≥vl or vl=0. Writing a result narrower than FLEN sets all upper bits to 1 for a valid NaN box.
- V supports FP32/FP64 and depends on F/D; this move at SEW=16 requires Zvfh. The animation shows finite-value bit copies at SEW=FLEN=64 without FP flags.
- Require valid vtype, supported FP widths and matching scalar FP extensions, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0 or for operations that do not round; vxrm does not control FP operations.
Pitfalls / Common Confusions
Only element 0 is copied, not the whole vector; the move still executes when vstart >= vl or vl=0.
The destination is a floating-point scalar register; the integer version is VMV.X.S.